Specifications

815F
Signal Register FIFO, upper
Certain of these registers, and a few additional registers, are also mapped into
the VXIbus A16 address space as 16-bit registers. These registers begin at a
base related to the EPC-2's logical address. This base is given by
11uu uuuu uu00 0000
where uuuuuuuu is the EPC-2's .i.unique logical address; (.i.ULA;). The EPC-2
is a VXI .i.DC device; (.i.dynamic configuration;), meaning that after a system
reset, its ULA is FFh, and it only responds to A16 accesses at the resultant
base FFC0h and beyond if the MODID line is asserted. Once the EPC-2 is assigned
a ULA, uuuuuuuu becomes this new ULA (whose value appears in the ULA register).
The mapping of registers in the A16 space is shown below. For registers that
are also accessible from within the EPC-2 via an I/O address, the I/O address is
given in parentheses.
Offset Upper byte Lower byte
0 ID (8141) ID (8140)
2 Device type (8143) Device type (8142)
4 Status/control (8145) Status/control (8144)
6 Slave offset (8147) Slave offset (8146)
8 Protocol/signal (8149) Protocol/signal (8148)
A Response (814B) Response (814A)
C Message high (814D) Message high (814C)
E Message low (814F) Message low (814E)
14 .i.Shared memory pointer; high
16 Shared memory pointer low
18 .i.Alternate response register;
Where a bit position has been described by a 0 or 1, the bit is a ROM bit, and
writing to it has no effect. Unless otherwise noted below, all registers and
bit values are readable and writeable.
.i.EXMID Driver Register; (EPC-2x only)
1 1 1 1 1 1 1 EXMI
96
This write-only register is used to assert a -.i.EXMID signal; to the EXM slot.
When EXMI=0, the ÄEXMID signal is asserted; when EXMI=1, it is not asserted.
.i.Memory Mapping Registers;
81xx
These registers are used by the EPC-2's BIOS to create the memory map described
at the beginning of this chapter. Their function is not described in this
manual.
.i.VME A21-14 Address Registers;
VMEbus Address bits 21-14
8130/
2/4/6
When an access is performed by the EPC-2 in its ".i.E page;" (address range
0E0000-0EFFFF), the access is mapped onto the VMEbus (VXI data transfer bus).
The least-significant 14 of the VME address bits are provided directly (from the
386). The remaining 2 (for an A16 access), 10 (for an A24 access), or 18 (for
an A32 access) bits must come from somewhere else. Eight of them come from
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