Specifications

VXIbus Interface
77
Trig Interrupt Enable Reg TTI7 TTI6 TTI5 TTI4 TTI3 TTI2 TTI1 TTI0 8164
This is a mask of the interrupt conditions in the trigger latch register. A 1 denotes
that the corresponding interrupt is enabled. If any bit in this register is a 1 and the
corresponding bit in the trigger latch register is a 1, the EPC-7 IRQ10 interrupt is as-
serted. Software may then examine the interrupt state register, event state register,
and trigger latch register to determine the cause.
The following registers are mapped as offsets from the EPC-7's VXI A16 base
address.
15 0
A24 Shared Mem Ptr High xx10
15 0
A24 Shared Mem Ptr Low xx12
15 0
A32 Shared Mem Ptr High xx14
15 0
A32 Shared Mem Ptr Low xx16
These registers form a 32-bit address register for the optional shared-memory
protocol. There are only a total of 32 physical register bits. If bit A32 in the ID
register is 1, the shared-memory register is mapped at offset 14 in the EPC-7's register
space in the VXI A16 address space. If A32=0, the register is mapped at offset 10.
Page 65
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com