Specifications

EPC-7 Hardware Reference
77
TTL Trigger Latch Register TTL7 TTL6 TTL5 TTL4 TTL3 TTL2 TTL1 TTL0 8161
This register catches assertions of the TTL trigger that last longer than 30 ns. A read
of the register returns the latched contents and clears the latches immediately
thereafter. The duration of the clear pulse is 125 ns.
This register is intended for use in implementing the asynchronous trigger protocol
defined in the VXI specification. Note that the register should be read repeatedly
until it is seen to be cleared. The register is not cleared by reset.
Clock Control Register 1 1 1 1 1 1 1
ENXC 8162
ENXC has meaning only when the EPC-7 is configured as the slot-0 controller. If
ENXC is set (1), the clock source attached to the CLOCK10 input on the front panel
is used to drive the VXI CLOCK10 signal on the backplane. If ENXC is 0, the VXI
CLOCK10 signal on the backplane is driven by an internal 10 MHz clock having an
accuracy of ± 100 ppm.
A write to this register will cause the CLOCK10 signal to stay in the high state for the
duration of the I/O write cycle to meet the requirements of rule B.6.4 of the VXI
specification.
If ENXC is set and there is no external clock source connected, it cannot be cleared
by writing 0 to the register; a hardware reset will be necessary. This provides a way
to test for the presence of the external clock signal. To do so, (1) set ENXC to 1, (2)
try to write 0 to EXNC, (3) read EXNC; if 1, issue a warning message and request
that the system be reset; if 0, set ENXC back to 1.
External Trigger Register 1 1 1 1 OUT Trigger-line 8163
This register controls the external TTL trigger connector on the front panel.
OUT If set (1), the external trigger is an output. If 0, the external trigger is
an input.
Trigger-line Specifies the TTL trigger line from the backplane to be connected to
the external trigger connector. 000 specifies TTLTRG0, ..., 111
specifies TTLTRG7.
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