Specifications
EPC-7 Hardware Reference
77
VME Event State Register 1 1 VXRCP SIGR WDT ACFA BERR SYSF 8154
Similar to the interrupt state register, this register defines additional conditions that
may result in an IRQ10 interrupt. If the bit is 0, the condition is present.
VXRCP A reset has occurred. This is a copy of bit VXR in the ECL trigger/misc
register. It provides a way to generate an interrupt because of certain reset
conditions.
SIGR Signal register FIFO is not empty.
WDT The EPC-7 watchdog timer period has expired.
ACFA VXIbus ACFAIL is asserted.
BERR An access from the EPC-7 to the VXIbus was terminated with a BERR (bus
error).
SYSF VXIbus SYSFAIL is asserted.
VME Event Enable Reg DSOR VWR
VXRCP SIGR WDT ACFA BERR SYSF 8155
The low-order six bits are a mask of the interrupt conditions in the event state
register. A 1 denotes that the corresponding event is enabled as an interrupt. If any
bit in this register is a 1 and the corresponding bit in the event state register is a 0, the
EPC-7 IRQ10 interrupt is asserted. Software may then examine the interrupt and
event state registers to determine the cause.
The following two bits are read-only state bits:
DSOR Clear whenever either of the VXI DS0/DS1 data strobes is asserted.
DSOR=0 thus indicates a data transfer in progress.
VWR When DSOR is 0, VWR=0 indicates that the data transfer is a write
operation.
TTL Trigger Sample Reg TTS7 TTS6 TTS5 TTS4 TTS3 TTS2 TTS1 TTS0 8156
This read-only register contains the state of the eight TTL trigger lines on the VXI J2
backplane. A 1 denotes an asserted trigger. Note that this register does not
necessarily match the value in the TTL drive register because of the open-collector
nature of the trigger lines.
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