Specifications

VXIbus Interface
This ability is also useful in system checkout (i.e., checking operation of the
backplane) and in giving an EPC-7 program the ability to view its memory in big
endian format.
A24 and A32 slave accesses result in accesses to the on-board DRAM and never to
the cache. Because the EPC-7's cache is a write-through cache, there is never a
discrepancy between data in the cache and the DRAM. When a slave access results
in a write into the DRAM, the EPC-7 automatically purges the cached entry, if it
exists.
Given the above, another subtle use for the ability of the EPC-7 to access its own
DRAM via a VMEbus access is selective purging of the cache. For instance, if the
EPC-7 is mapped at address base 18000000h in the A32 space and a program is
meant to purge location 0000AB00h from the cache, a read from 0000AB00h
followed by a write of the read data back to 1800AB00h will accomplish the task.
Read-Modify-Write Operations
VMEbus RMW (read-modify-write) cycles can be performed through use of the
LOCK instruction prefix with certain instructions. All of these instructions perform a
read followed by a write. When such a read occurs that is mapped to the VMEbus,
the EPC-7 treats it as the start of a VME RMW cycle. The next VME access from the
CPU is treated as the write that terminates the RMW cycle. Keep in mind that
accesses that cross a 32-bit boundary are actually performed as two accesses. For this
reason, RMW accesses that cross a 32-bit boundary will not behave as expected.
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The EPC-7 provides synchronization integrity in its local DRAM between accesses
from the CPU into the DRAM and RMW VME accesses from other masters into the
DRAM.
When a VMEbus slave read access occurs to the local DRAM, the EPC-7 watches the
VMEbus data and address strobes to determine if the cycle is an RMW cycle. If it is,
accesses by the CPU are held up until the terminating access of the RMW cycle
occurs.
When the CPU performs a locked access (e.g., via an instruction using the LOCK
instruction prefix) to the local DRAM or the cache, VMEbus slave accesses are held
up until the last locked access completes.
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