Specifications

BB
Appendix B: I/O Map
I/O Map
The following defines the I/O addresses decoded by the EPC-7. It does not define
addresses that might be decoded by EXMs in the EPC-7.
Port Functional group Usage
00 DMA Channel 0 address
01 Channel 0 count
02 Channel 1 address
03 Channel 1 count
04 Channel 2 address
05 Channel 2 count
06 Channel 3 address
07 Channel 3 count
08 Command/status
09 DMA request
0A Command register (R)
Single-bit DMA req mask(W)
0B Mode
0C Set byte pointer (R)
Clear byte pointer (W)
0D Temporary register (R)
Master clear (W)
0E Clear mode reg counter (R)
Clear all DMA req mask(W)
0F All DMA request mask
20 Interrupt controller 1 Port 0
21 Port 1
24 83000 Controller Data register
26 Index register
40 Timer Counter 0
41 Counter 1
42 Counter 2
43 Control (W)
60 Keyboard controller Data I/O register
61 NMI status NMI status
64 Keyboard controller Command/status register
70 Real-time clock RTC index reg / NMI enable
71 RTC data register
0 seconds
1 seconds alarm
Port Functional group Usage
2 minutes
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