Specifications

5
Hardware Management
60
Updatechannel0isconsideredthe“fastpath”updateportandconnectstheAMCbay
port12totheZone2connector.ItisE‐Keyed(enabledordisabled)throughasetof
differentialbuffersthatarecontrolledbytheIPMC.Updatechannel4isconsideredthe
“slowpath”updateportandconnectstheAMCbayport13totheZone2connector.The
“slowpath”isE‐K eyedwithsingle‐endedTTL‐levelbuffers.Thebackplaneconnectsthe
updatechannelstoanadjacentphysicalslotandprovidesoperationalredundancyacross
thebackplane.
TheRTMhastwox4PCIExpressportsthatrequireE‐keyingaspartofthehotswap
handshakingthatmusttakeplacebetweentheMMContheRTM,theIPMC,andtheI/O
hub.Ports17‐20ontheAMCaredirectlyconnectedbetweentheAMCba yandtheRTM.
AMCbayport15alsoroutesdirectlytotheRTMforI
2
CandRS‐232.TheE‐keyingforthese
portsiscontrolledbytheMMContheRTMandtheAMC.
Table 16andTable 17onpage 60listI/OchannelsfromtheIPMCthatprovideE‐Key
controlforeachchannelandportoftheFabricinterface,updatechannel,and
synchronizationclocks.
Table 16. Fabric interface I/O E-Key descriptions
Fabric
channel
a
a
Fabric channels 3 through 15 are not used on the CPM.
Port 0
control
Port 1
control
Port 2
control
Port 3
control
Comments
1 IPMC IPMC IPMC IPMC Connected through an Ethernet controller to the CPU.
2 IPMC IPMC IPMC IPMC
Table 17. Update channel and synchronization clock E-Key descriptions
Channel Controlled by Comments
Update channel 0 IPMC PMC8380 (shared with SAS multiplexer) between AMC bay port 12
and backplane update channel 0
Update channel 1 IPMC Not used
Update channel 2
Update channel 3
Update channel 4 IPMC TTL-Level buffers between AMC bay 1 port 13 and update channel 4
Synchronization clock 1A Always disabled 8-KHz clock input from backplane
Synchronization clock 1B
Synchronization clock 2A Always disabled 19.44-MHz clock input from backplane
Synchronization clock 2B
Synchronization clock 3A IPMC, CPU
Disabled by
default; enabled
by E-Key when a
supported
device function
is detected.
AMC synchronization clock output to backplane.
IPMC has global control of whether clocks are driven.
CPM has control of which clock (CLK3A or CLK3B or none) is driven.
Synchronization clock 3B