Specifications

5
Watchdog timers
57
Watchdog timers
TheCPMprovidesfourwatchdogtimers(seeTable 15)tohelppreventtheboardfrom
enteringanunrecoverablestate.TheIPMCandtheIPMCFPGAprovidethewatchdog
timers.Figure 12illustrateswhenandhowtheCPMenables,resets,anddisables
watchdogtimers.
Figure 12. Watchdog timer operation
BIOS stops watchdog and
configures BMC watchdog
as OS load watchdog
OS may stop watchdog
and may configure and
feed SMS/OS
BMC Watchdog (WD 1)
OS
BIOS
Corrupt Flash
Detection watchdog
IPMC watchdog (WD 2)
Time
IPMC strobed
every 2 seconds
IPMC watchdog
enabled with 10
second timeout
IPMC boots and
changes timeout to
6 seconds
IPMC
(H8_RESET)
de-asserted
IPMC power up
(P3V3_STBY)
IPMI command from
BIOS to disable
CFD watchdog
Payload power
enabled (+12V)
BIOS configures BMC
watchdog as POST
watchdog timer
Table 15. Watchdog timer locations and controls
Watchdog Location Fed by Action
IPMC watchdog (WD 2) IPMC FPGA IPMC Resets and isolates the IPMC block
Corrupt Flash Detection (CFD) watchdog IPMC CPU Power cycle, followed by boot from secondary SPI
flash device
BMC watchdog (WD 1) IPMC CPU Configurable
(no action/hard reset/power cycle/power down)