Specifications

4
Super I/O chip
39
TheICHSMBusconsistsofatransmitdatapathandhostcontroller.Thetransmitdatapath
providesthedataflowlogicneededtoimplementthesevendifferentSMBuscommand
protocolsandiscontrolledbythehostcontroller.TheRTCclockstheICHSMBuscontroller
logic.
Thehostcontroller’s programmingmodelhastwosegments:aPCIconfigurationanda
systemI/Omapping.Allstaticconfigurations,suchastheI/Obaseaddress,areconfigured
viathePCIconfigurationspace.Real‐timeprogrammingofthehostinterfaceisdonein
systemI/Ospace.
Super I/O chip
AWinbondW83627superI/Ochipprovidesdualserialportsandvoltagemonitorstothe
CPU.OntheCPM,thesuperI/OisconnectedtotheICHthroughtheLPCbusandisused
primarilyforserialconnectivityandvoltagemonitoring.
BothoftheCPMCOMportsareconnectedtothe
COMuxCPLD.Theserialconnectionto
thefrontpanel(COM1)supportsdualhardwarehandshakingandimplementsthe
followingsignals:TXD,RXD,DTR,RTS,DSRandCTS.TheserialconnectiontotheRTM
(COM2)supportsTXDandRXDonly.Softwarehandshakingispossible.
TPM chip
TheTrustedPlatformModule(TPM)chipisasecuritykeygeneratorandakeycache
managementdeviceforstoringsecurecryptographickeys.TheTPMmoduleisaccessible
throughtheLPCbus.
TheBIOSTPMcodeisinvokedatspecificinstancesduringPOSTbootexecution,and
providesintegrityauthenticationduringthebootprocess.
SAS and SATA
TheSASandSATAconnectionsarediagrammedinFigure 7onpage 40.
SAS
AnRTMsuchastheATCA‐5400isrequiredforaSASconnectionbecausetheSAS
controllerisontheRTM.ASASharddiskdrivecannotbeusedonaninstalledAMCunless
theRTMispresent.
SATA
TheSATAcontrollerresidesontheCPM,soanRTMisnotrequired.AninstalledAMCcan
useaSATAharddiskdrive,butaSASdriveisnotsupportedfortheAMC.