Specifications
4
Components and Subsystems
38
Real-time clock
TheICHincludesanintegratedreal‐timeclock(RTC)thatkeepstrackofthetimeofday
anddate.TheRTCcircuitryincludes256bytesofcapacitor‐backedCMOSRAM.TheRT Cis
derivedfroma32.768KHzcrystalwiththefollowingspecifications:
• Frequencytolerance@25°C:±20ppm
• Frequencystability:maximumof‐0.04ppm/(°C)
2
•AgingF/f(firstyear@25°C):±3ppm
•±20ppmfrom0‐55°Candaging1ppm/year
Whenpowerisremovedfromtheboard,thetimeanddatearemaintainedbyan
electrolyticcapacitorforuptotwodays.Whenthechassisisturnedon,theRTCgets
powerfromtheIPMI3.3Vpowersupply,whichallowsthecapacitortobegincharging
beforetheCPMpayloadpoweristurnedon.
RTC date ranges and default initial dates
ThefollowingarevaliddaterangesanddefaultinitialdatesthatcanbesetintheRTC
throughtheBIOS.ValuesvarybasedontheBIOSversion.
•BIOSversion01.01.32andbelow:
Validdaterange:01/01/2005‐12/31/2099
Defaultinitialdate:01/01/2005
•BIOSversion01.01.33andabove:
Validdaterange:01/01/1998‐12/31/2099
Defaultinitialdate:01/01/2005
SeethehelpsectionintheBIOSSetupmainmenuforassistancesettingthedateforthe
RTC.
SMBus controller and multiplexers
TheICHincludesaSMBus2.0‐complianthostcontroller,whichallowstheCPUtoinitiate
communicationwithSMBusslaveperipheralsandI
2
C‐compatibledevices.TwoSMBus
multiplexersgivetheIPMCaccesstotheICHslaveregistersandtotheDIMMtemperature
sensors.RefertoI
2
CandSMBusmaponpage 163forinformationonthedevices
connectedtotheSMBus.
TheslaveinterfaceallowsanexternalmastertoreadfromorwritetotheICH.Writecycles
canbeusedtocausecertaineventsortopassmessages.Readcyclescanbeusedto
determinethe
stateofvariousstatusbits.TheICH’sinternalhostcontrollercannotaccess
theinternalslaveinterface.