Specifications

USB controller

TheICHcontainstwouniversalhostcontrollerinterface(UHCI)controllersandtwo

enhancedcontrollerhostinterface(EHCI)controllersthatsharethesamesetofpins.Each

pairofcontrollersprovidesuptotwelveUSB1.1orUSB2.0ports.EachEHCIportallows

datatransfersupto480Mb/sandreportsover‐currentstatusbacktotheICH.

TheCPMprovidesthefiveportslistedinTable 6whenconfiguredforEHCI(USB2.0):

SATA controller

TheICHincludestwoSATAhostcontrollersthatsupportdatatransferratesofupto3.0

Gbps.CommunicationovertheSATAbuscanoperateinoneoftwodifferentmodes,

dependingonoperatingsystemrequirements:

•Innativemode,bothcontrollersareusedtoimplementuptosixSATAports.Ports0‐3

arehandledbythefirstcontrollerandports4‐5arehandledbythesecondcontroller.

•Inlegacymode,onlyports0‐3areavailablefromthefirstcontroller.

ForinformationaboutSAS/SATAswitchingcontrol,refertoSASandSATAonpage 39.

SPI bus

TheICHusesaserialperipheralinterface(SPI)busforcommunicationwiththetwoboot

flashdevices.ThisconnectionisdiscussedinmoredetailunderRedundantbootflash.

LPC bridge

TheICHenablescommunicationbetweentheCPUandlow‐bandwidthperipheralsby

providingalowpincount(LPC)bridgeconnectiontothefollowingdevices:

•SuperI/O(seeSuperI/Ochip)

•CPUcomplexFPGA(seeCPUcomplexFPGA)

•IPMC(seeIntelligentPlatformManagementController)

TheLPCbridgeimplementsallofthecyclesdescribedintheIntelLowPinCountInterface

Specification,Revision1.1.

Table 6. USB 2.0 ports

Port Number Port Location Notes

0 Front panel, upper USB port Refer to Front panel connectors on page 26 for additional

information.

1 Front panel, lower USB port

2 No external port connections USB NAND flash A and B. User flash is discussed under

Redundant user flash.

4 RTM USB port Refer to Rear transition module (RTM) interface on page 29.