Specifications

4
Quick path interconnect
33
2x refresh mode
TheCPUdoublestherefreshratetothememorychannelstobetterpreservethedata
whentheDRAMisoperatingatelevatedtemperatures.TheDRAMcomponentshavetwo
temperaturelimits:T32andT64.T32isthetemperaturelimitfora1xrefreshrate.T64is
theupperDRAMtemperaturelimitwhenoperatingin2xrefreshmode.WhenT64is
exceeded,anSMI(systemmanagerinterrupt)isgeneratedbecausetheDRAMisoperating
outofspecification.ForatypicalDDR3DRAMcomponent,T32is85°CandT64is95°C.
Thedoublerefreshratecanbedisabledbychangingthesettingto1xrefreshintheBIOS.
Quick path interconnect
TheCPUincludestwopoint‐to‐pointIntelQuickPathinterconnectinterfaces(QPI)for
communicationbetweentheCPUandtheI/Ohub.However,theCPMusesonlyoneQPI
interfacefromtheCPU(QPIport1).TheQPIinterfaceis20laneswideunderfull
operation.Withitsintegratedmemorycontroller,theCPUincorporatestheQPIcaching
agentsformaintainingcachecoherenceaswellasthehomeagentsformanagingaccess
tomemoryregions.Dataofanywidthisconvertedtopacketsandthensentseriallyover
theQPIlink(seeTable 4).
Memory and storage devices
TheCPMprovidesthefollowingmemorydevices:
•SocketsforinstallingDDR3DIMMs.SeeDDR3SDRAMformoreinformation.
•Two16MB(redundant)SPIflashmemorychipsdedicatedtoBIOSandbootoperations
(seeRedundantbootflash).
• PluggableeUSBmodulesforuserflashmemory(seeRedundantuserflash).
ThesedevicesprovideadditionalstorageoptionsfortheCPM:
•aSFFflashdriveontheAMC
•alocalSFFSASharddiskdriveontheRTM,whichincludesastoragecontrollerfora
hardware‐basedredundantarrayofinexpensiveharddiskdrives(RAID)
• iSCSIstorageoverboththeBaseandFabricinterfaces