Specifications

E
APIC interrupt mapping
159
APIC interrupt mapping
Table 52liststheAPICinterruptmappingfortheCPM.
Table 52. APIC interrupt mapping
ICH APIC IRQ# Source Interrupt ICH input Shared?
IRQ0 Cascade from 8259 #1 N/A Internal
IRQ1 USB keyboard controller INT9 Internal No
IRQ2 8254 counter 0, HPET #0 N/A Internal
IRQ3 (data frame 4) Super I/O COM2 SERIRQ No
IRQ4 (data frame 5) Super I/O COM1 SERIRQ No
IRQ5 (data frame 6) RTM (future RTM) RTM_INT0 SERIRQ (from
CPU complex
FPGA)
No
IRQ6 (data frame 7) IPMC Message Interrupt SERIRQ No
IRQ7 (data frame 8) RTM (future RTM) RTM_INT1 SERIRQ (from
CPU complex
FPGA)
No
IRQ8 RTC, HPET #1 N/A Internal
IRQ9
IRQ10 (data frame 11) TPM SERIRQ SERIRQ No (BIOS or
SW must
program)
IRQ11 HPET #2 N/A Internal No
a
a
If used for HPET, no interrupt sharing is allowed.
IRQ12 HPET #3 N/A Internal No
1
IRQ13
IRQ14 SATA PRIMARY (legacy
mode)
N/A Internal No
IRQ15
IRQ16 CPU complex FPGA SOC_INT_N PIRQA# No
IRQ17 PCI9030 INTA# PIRQB# No
IRQ18 CPU complex FPGA CS_INT_N PIRQC# No
IRQ19 CPU complex FPGA N/A PIRQD# No
IRQ20 CPU complex FPGA COUNT_INT_N PIRQE# No
IRQ21 CPU complex FPGA CLOCK_INT_N PIRQF# No
IRQ22 IPMC Optional payload interrupt PIRQG# No
IRQ23 CPU complex FPGA FPGA_INT_N PIRQH# No
N/A (data frame 3) IPMC SMI SERIRQ No