Specifications

E
Low-Level Hardware Map
158
Interrupts
ThissectiondescribesI/Ocontrollerhubinterrupts,APICinterruptmapping,andPIC
interruptmapping.
I/O controller hub interrupts
TheI/Ocontrollerhub(ICH10R)hastwobuilt‐ininterruptcontrollers:the8259
ProgrammableInterruptController(PIC)andtheAdvancedProgrammableInterrupt
Controller(APIC).TheICHacceptsinterruptsfromthefollowingsources:
•PIRQ[D:A]#–PCIinterruptrequests
• PIRQ[H:E]#–PCIinterruptrequests
•SystemControlInterrupt(SCI)
•InternalHighPrecisionEventTimer(HPET)
•SerialIRQ(SERIRQ#)
ThePICimplementstwo8259sthatprovideISA‐compatibleinterruptsforsystemtimer,
serial/parallelports,keyboardcontroller,mouse,floppydisk,andDMAchannels.In
addition,the8259cansupportPCIinterruptsiftheyaremappedontothecompatibleISA
interruptlines.
TheAPICprovides24interruptsandhandlesinterruptrequeststhroughmemoryaccesses
ontheCPUdatapath.Interruptprioritiescanbereassignedbasedontheendapplication.