Specifications

C
Connector Pinouts and Jumper Settings
146
RTM interface pinout
Zone 3 J30 connector pinout
Zone 3 J31 connector pinout
Table 45. RTM connector J30 signals
Row AB CD EF GH
1 +12V_RTM +12V_RTM +12V_RTM +3.3V_IPMC RES_STATE RTM_PRSNT* RTM_HS_LED RTM_EN*
2 +12V_RTM +12V_RTM +12V_RTM IPMC_INT* IPMC_I2C_CL
K
IPMC_I2C_DA
T
USB_D+ USB_D–
3 SERIAL_0_TX SERIAL_0_RX JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TCK JTAG_TRST*
4 SOCA SOCB INT_0 INT_1 RTML_TX RTML_RX RTML_CLK RTM_RESET
5 SERIAL_1_TX SERIAL_1_RX
6 CPU0_SCL
(SMB_SCL)
CPU0_SDA
(SMB_SDA)
7
8
9 SAS0_TX+ SAS0_TX– SAS0_RX+ SAS0_RX– SAS1_TX+ SAS1_TX– SAS1_RX+ SAS1_RX–
10 GE1_TX+ GE1_TX– GE1_RX+ GE1_RX– GE0_TX+ GE0_TX– GE0_RX+ GE0_RX–
Note: Each differential pair has an individual L-shaped ground contact (not listed).
Gray indicates unused pins
Table 46. RTM connector J31 signals
Row AB CD EF GH
1 AMC_17_TX+ AMC_17_TX– AMC_17_RX+ AMC_17_RX– AMC_18_TX+ AMC_18_TX– AMC_18_RX+ AMC_18_RX–
2 AMC_19_TX+ AMC_19_TX– AMC_19_RX+ AMC_19_RX– AMC_20_TX+ AMC_20_TX– AMC_20_RX+ AMC_20_RX–
3
4
5 PCIE1_RX2+ PCIE1_RX2– PCIE1_TX2+ PCIE1_TX2– PCIE1_RX3+ PCIE1_RX3– PCIE1_TX3+ PCIE1_TX3–
6 PCIE1_RX0+ PCIE1_RX0– PCIE1_TX0+ PCIE1_TX0– PCIE1_RX1+ PCIE1_RX1– PCIE1_TX1+ PCIE1_TX1–
7
PCI1_REFCLK
+
PCI1_REFCLK
–
PCI0_REFCLK
+
PCI0_REFCLK
–
8 PCIE0_RX2+ PCIE0_RX2– PCIE0_TX2+ PCIE0_TX2– PCIE0_RX3+ PCIE0_RX3– PCIE0_TX3+ PCIE0_TX3–
9AMC1_I2C_S
CL
AMC1_I2C_S
DA
SFP1_I2C_SC
L
SFP1_I2C_SD
A
SFP0_I2C_SC
L
SFP0_I2C_SD
A
10 PCIE0_RX0+ PCIE0_RX0– PCIE0_TX0+ PCIE0_TX0– PCIE0_RX1+ PCIE0_RX1– PCIE0_TX1+ PCIE0_TX1–
Note: Each differential pair has an individual L-shaped ground contact (not listed).
Gray indicates unused pins