Specifications

B
IPMI Commands and Managed Sensors
124
Temperature sensor details
This section describes temperature sensors which require initial configuration support or a
handshake mechanism with the X86 processor complex. It also explains the presentations for
sensors with reported readings different from other traditional temperature sensors.
SPD DIMM DDR3 temperature sensors (07h – 0Eh)
When memory modules containing serial EEPROMs are detected with the thermal sensors and
Serial Present Detect (SPD) circuit, the CPM monitors up to eight SPD DIMM DDR3 sensors and
reports the sensor measurements in degrees centigrade.
The CPM uses the SMBUS_FREE* signal to arbitrate the memory access with the X86 processor
complex through a multiplexer on I
2
C bus 3. The IPMC controls the select input to the MUX, but it
qualifies its control with a handshake signal from an ICH10R GPIO. When the CPM initially powers
up, the I
2
C bus 3 DIMM multiplexer is configured to allow the X86 processor complex to have access
to the DIMMs. After all SPDs are read, the X86 processor complex asserts SMBUS_FREE* (GPIO)
to indicate it is finished. The IPMC selects I
2
C bus 3 to access the DIMMs about every 250 ms as
part of the round robin sensor scan.
The CPM has individual access to each of these temperature sensors via a series of I
2
C addresses
ranged between 0x30 and 0x3F for SPD slots A0, A1, A2, B0, B1, B2, and C0, C1.
CPU Core DTS temperature sensor (11h)
The CPM acquires the CPU core DTS (digital temperature sensor) reading from the PECI bus using
a PECI-to-I
2
C translator available at address 0x54 on I
2
C bus 2. The PECI reading indicates how far
the current CPU temperature is from the internal thermal control circuit activation point where the
PROCHOT event is issued.
The CPM presents the CPU core DTS temperature sensor readings as negative units in the range of
[0, -128] below the internal thermal throttle temperature.
3 The cause of reset.
[7:0]:
00h = CFD Timer was initialized (occurs any time a reset is asserted to
the payload processor)
01h = CFD Timeout has occurred (causes the IPMC firmware to disable
payload power, select the secondary boot flash, then re-enable payload
power to boot from the secondary SPI flash)
02h = Flash bank switch was externally initiated
03h = No change
Table 37. OEM Active Boot Flash sensor event data format
Event Data Data Field