Specifications

B
IPMI Commands and Managed Sensors
102
RTM Reset Button
Instructs the H8 IPMI firmware to perform a cold reset.
Set Payload Status
Informs the H8 IPMI firmware about the current payload processor status. The IPMI firmware uses
the reported information to initiate its internal processes, which are dependent on resources
controllable by the onboard x86 processor complex.
Boot phases 1 and 4 specified in status byte 1 report respectively the commencement and
completion of the onboard x86 processor complex boot-up processes. The remaining boot phases
may optionally report other milestones in the payload boot-up process.
When boot phase 1 is received, the IPMI firmware initializes all appropriate control signals to yield
access of all hardware shared resources to the onboard x86 processor complex. When boot phase 4
is received, the IPMI firmware reconfigures the appropriate control signals to regain access of all
hardware shared resources and commences the applicable management functions.
NetFn 0x2E
Cmd 0x15
Data field Byte 1 Radisys IANA PEN0: F1h
Byte 2 Radisys IANA PEN1: 10h
Byte 3 Radisys IANA PEN2: 00h
Response field Byte 1 Completion code
Byte 2 Radisys IANA PEN0: F1h
Byte 3 Radisys IANA PEN1: 10h
Byte 4 Radisys IANA PEN2: 00h
NetFn 0x2E
Cmd 0x20
Data field Byte 1 Radisys IANA PEN0: F1h
Byte 2 Radisys IANA PEN1: 10h
Byte 3 Radisys IANA PEN2: 00h
Byte 4 Command Version: hard coded to 0x00
Byte 5 Status Byte 1
Bits 7:4 = Reserved
Bit 3 (Boot Phase 4) = 0b (Not Complete) 1b (Complete)
Bit 2 (Boot Phase 3) = 0b (Not Complete) 1b (Complete)
Bit 1 (Boot Phase 2) = 0b (Not Complete) 1b (Complete)
Bit 0 (Boot Phase 1) = 0b (Not Complete) 1b (Complete)