Specifications

2
Hardware Description
40
IPMC watchdog timer (Watchdog 2)
TheIPMCFPGAincludesahardwarewatchdogtimer,Watchdog2.Thiswatchdogisenabled
bydefaultandwillstartrunningassoonas+3_3V_SUSpowerispresentandtheFPGAhas
loadeditsinternalflashimageintoitsinternalSRAM.Thedefaulttimeoutonpower‐upis10
seconds.AftertheIPMCboot‐loaderisfinished,theIPMCreprogramsthetimeoutfor6
secondsandwillcontinuetostrobeevery2seconds.Ifafirmwareorhardwareproblemon
theIPMCcausesittostopstrobingthewatchdogtimerintheIPMCFPGA:
1. TheIPMCisautomaticallyisolatedfromtheIPMB‐A,IPMB‐BandIPMB‐Lbusessothat
theyremainfunctionalfortheremainingbladesinthechassis,
2. Watchdog2forcesaresetoftheIPMC.
Power subsystems
AllCPMpowerissuppliedthroughtheP10backplaneconnectoras‐48VDC,asspecifiedby
thePICMG3.0specification.TheuseofDCpowerminimizesthepossibilityofRFIandEMI
interferencefortheon‐boardandboard‐to‐boardsignalsinATCAcomponents.Figure 6
showsthepowerarchitectureanddistributionfortheCPM.
Input protection and monitoring
Eachofthemainpowerfeeds(‐48A/B)andreturnfeeds(VRTNA/B)oftheCPMisprotected
bya10Afast‐blowfuse.ThisprotectstheCPMcircuitryintheeventpowerdrawex ceedsthe
rated350Wpowerbyasignificantamount.Inaddition,theENABLE_A/Binputstothepower
inputmodule(PIM)areeachprotectedby100mAfuses.
TheCPMdoesnotmonitorinputvoltagedirectly,buttheIPMCdoesdetectinputvoltage
presenceattheZone1connectorandcomparesitwiththePIM_STATUSsignal.Anystatus
differenceindicatesoneormoreinputfuseshaveblown.