Specifications

2
Hardware Description
37
TheCX3hasiSCSIandPXEbootsupportenabledintheSPIflashfirmware.iSCSIandPXE
cannotbeenabledatthesametime;thedesiredfunctionmustbeselectedintheBIOSsetup
menu.
Clock synthesizer subsystem
CPMusestwomajorcomponents,aCK420BQandaDB1900Ztogeneratetheclocksignals
usedbytheCPUs,bythePCH,andbyotherperipheralcomponents.
TheCK420BQclockgeneratorprovideshost,chipset,PCIandLPCperipheralclocksonthe
CPM.Thedeviceusesa25.0000MHzreferencecrystalandreceivescontrolinputfromthe
BIOSovertheSMBus.TheclocksignalsaresuppliedtotheCPUs,thePCH,theTPM,theIPMC,
andtheCCFPGA.
TheDB1900Zdifferentialbufferdistributes100MHzclockstothePCIExpressandQPIdevices.
TheclocksoutputbythisdevicearebasedonareferenceclockfromtheCK420BQclock
generator.InadditiontothePCIeandQPIclocks,thisdevicesuppliesref erenceclocksforthe
MellanoxCX2/CX3andIntelI350GbEcontrollers,theRTMPCIeinterfaces,andtheMXM
connector.
Inadditiontotheabovereferenceclocks,thefollowingoscillatorsorcrystalsareprovidedon
theCPM:
•A40.000MHz100ppmoscillatorisprovidedfortheCCFPGA.
•TheCCFPGAprovidesa6.6MHzclockfortheRTMLinterfacetotheRTM.
•A32.768kHzcrystalisprovidedforthe PCHRTC.
•A32.768kHzcrystalisprovidedforthe IPMCRTC.
•A32.768kHzcrystalisprovidedforthe TrustedPlatformModule.
•A25.000MHz30ppmcrystalisprovidedfortheCK420BQ
•A25.000MHz30ppmcrystalisprovidedfortheI350quadGbEcontroller
•A32.000MHz50ppmoscillatorisprovidedfortheIPMCFPGA
•A156.25MHz50ppmoscillatorisprovidedfortheMellanox
CX340GEthernetcontroller
Reset subsystems
CPM9supportsthreetypesofreset:platformreset,powergoodreset,andmemoryretained
(MR)reset.
Platform reset
Aplatformreset(thePLTRST*signal)isdefinedasatotalsystemboardreset(exceptforIPMI
circuitry).Alldevicesandregistersareresettotheirdefaultstate.Afteraplatformresetall
datainDRAMmaybeinvalidduetotheCPUmemorycontrollerdiscontinuingrefreshcycles.
Memoryisthen
clearedduringthesystemBIOSinitialization.