Specifications

2
Hardware Description
34
CPU Complex (CC) FPGA
TheCCFPGAmoduleperformsanumberofsignificantmonitoringandinterfacefunctionson
theCPM.ManyofthesefunctionsareindicatedinFigure 1onpage 16.Thefollowingsections
providemoredetailsontheCCFPGAfunctions.
Power management and monitoring
MostoftheCPMpayloadpowersuppliesaremonitoredbytwoADM1066powersequencers,
buttheCCFPGAcontrolsthepowersequencingfortheCPM.Onpower‐up,itlooksatthe
payloadpowerenablefromtheIPMCtobeginthepowerupsequence.Whenbothpower
sequencershaveindicated“powergood”andtheexternalcomparatorsindicatein‐tolerance,
theCCFPGAassertsPWR_OKtothePCH.TheCCFPGAde‐assertsPWR_OKandassertsfault
signalswhenanymonitoredconditionfallsout‐of‐tolerance.
System Reset monitoring
TheCCFPGAmonitorsthesourceofallPowergood,Platform,andMR‐Resetsandprovidesa
16‐bitregisterforresetsour cemonitoring.WhentheCCFPGAdetectsanymonitoredreset,it
assertsaninterrupttotheIPMC.TheIPMCcanreadtheresetsourceregisterandthenclear
theinterrupt.RefertoResetsubsystemsonpage 37formoreinformation.
Dual UARTs, COM port, and SPI mux
Two16550‐compatibleUARTsareinstantiated intheCCFPGA.COM1andCOM2portscan
operateuptoa115200baudrate(defaultof115,200baud,8‐bit,noparity,1stopbit).TheCC
FPGAisabridgebetweentheSPIflashprogrammingheader,thePCHandtheredundant
64Mbflashdevices.
TheFPGAincludesfunctionalitytomultiplextheinternalUARTconnectionsbetweenthe
front/RTMexternalportsandtheSerialoverLAN(SOL)anddebugconsoleportsfromthe
IPMC.RefertoSerial‐Over‐LANonpage 65formoreinformation.
TheCCFPGAisabridgebetweentheSPIflashprogramming
header,thePCHandthe
redundant64‐Mbflashdevices.RefertoSerialPeripheralInterface(SPI)onpage 30formore
information.
LPC/I
2
C interfaces
TheCCFPGAusesanLPCinterfacetoprovidebyte‐wideread/writeaccesstotheinte rnal
FPGA.
I/Oport80hisusedtotransmitBIOSPOSTprogresscodesduringboot.TheCCFPGA decodes
port80writesfromtheBIOSandstoresthelastfourcodesinI/Oregisters.Thecodes
are
shiftedthroughtheregistersFIFO‐style,sothattheoldestcodeispushedoutwhenanew
codeisstored.
TheCCFPGAsupportsdual‐accesstoitsinternalI/OregistersbetweentheSMBusinterfaceto
thePCHandtoIPMCI
2
CBus3.Anarbiterpreventsdatalossorcorruption.