Specifications

2
Hardware Description
33
Management Engine (ME)
TheCPMManagementEngine(ME)usesNodeManager2.0firmwaretoperformpower
monitoring&alert,powerlimitingpolicies,thermalmonito ring&alert,andpowerreduction
tasksduringboot.AsdescribedinSerialPeripheralInterface(SPI)onpage 30aredundant
firmwareimageisstoredintheMEFlashincasetheMEfirmwareneedstoberecovered.
AsshowninFigure 5,theIPMCI
2
CBus5isconnectedtoSMLink0onthePCHtoallowthe
IPMCaccesstoCPUandDIMMtemperatureinformation,PCHtemperatureinformation,CPU
powerinformationandotherstatistics.
IPMI controller
TheIPMIcontroller(theIPMC) supportsan“intelligent”hardwaremanagementsystem,
basedontheIntelligentPlatformManagementInterfaceSpecification.Thehardware
managementsystemcanmanagethepower,cooling,andinterconnectneedsofintelligent
devices,monitorevents,andlogeventstoacentralrepository.
TheIPMCisaRadisys‐designedreusableentitybasedontheRenesasH8S/2472
microcontrollerandLatticeXP2FPGA.TheIPMCprovidesthefollowingfeatures:
•Anexternal16‐bitaddress/databuswithinternal32‐bitconfiguration
•InternalROM(512KBofFlashROM)andRAM(40KB)
•2MBexternalSPIBus‐basedFlashROM
• ControloffrontpanelLEDs(H/S,OSS,PWR,andAPP)
• MonitoringoffrontpanelReset,andHotSwapswitching
• Controlofthreebackplaneinterfaces(redundantIPMB‐A/Bbusesandanx8hardware
addressbus)
• ControllerforsixI
2
Cbuses(I
2
CBus0‐I
2
CBus5)
•Eightanaloginputs
•8‐bitparalleldatabus
• SixKCSLPCaddress/dataplusKCSLPCresetandclockinterfaces
•Threeserialports(SCI‐1/3/F)
•SPIbuscontrolledbySSCforadditionalFlashandFPGAsupport
•Eightgeneralpurpose,eightretainedstate,and90FPGAgeneralpurposeGPIOports
•OneEthernetand
oneUSBinterface
RefertoAppendixB,IPMICommandsandManagedSensors,onpage 86formoredetailed
informationontheIPMI sensors,data,andcommands.