Specifications

2
Hardware Description
31
SMBus/I
2
C bus
ThePCHprovidesanSMBushostcontroller(SMBus2.0compliant)aswellasanSMBus
secondaryinterface.ThehostcontrollerprovidesamechanismfortheCPUtoinitiate
communicationswithSMBusperipherals(master/slaveinterface).ThePCHalsocanoperate
inamodethatsupportscommunicationwithI
2
Ccompatibledevices.
Theslaveinte rfaceallowsanexternalmastertoreadfromorwritetothePCH.Writecycles
canbeusedtocausecertaineventsorpassmessagesandthereadcyclescanbeusedto
determinethestateofvariousstatusbits.ThePCHinternalHostControllercannotaccessthe
internalslaveInterface.
Table 8liststheSMBusandI
2
CdeviceaddressesontheCPM.
Table 8. SMBus and I
2
C bus device addresses
Device Bus Number Read Address Write Address
IPMC FPGA IPMC I
2
C bus 2 C1h C0h
CPU Complex FPGA IPMC I
2
C bus 2 B1h B0h
M41T82RM6E RTC IC IPMC I
2
C bus 2 D1h D0h
PCH SMLink0 IPMC I
2
C bus 5 45h 44h
PCH SMLink1 IPMC I
2
C bus 3 4Dh 4Ch
ADM1066 IPMC I
2
C bus 3 69h 68h
ADM1066 IPMC I
2
C bus 3 6Bh 6Ah
T0808P IPMC I
2
C bus 3 C3h C2h
MXM (possible address per spec) IPMC I
2
C bus 3 33h 32h
MXM (possible address per spec) IPMC I
2
C bus 3 57h 56h
MXM (possible address per spec) IPMC I
2
C bus 3 99h 98h
MXM (possible address per spec) IPMC I
2
C bus 3 9Fh 9Eh
I350(Base) LAN0 IPMC I
2
C bus 4 21h 20h
I350(Base) LAN1 IPMC I
2
C bus 4 23h 22h
I350(Front/RTM) LAN2 IPMC I
2
C bus 4 71h 70h
I350(Front/RTM) LAN3 IPMC I
2
C bus 4 73h 72h
CX3 (Fabric) IPMC I
2
C bus 4 49h 48h
RTM MMC IPMC I
2
C bus 5 GA[2:0] = GPU;
CK420BQ PCH Master SMBus D3h D2h
DB1900Z PCH Master SMBus D9h D8h
CPU Complex FPGA PCH Master SMBus D1h D0h