Specifications

Hardware Description

Serial ATA (SATA)

ThePCHincludestwoSATAhostcontrollersthatprovidesixSATA3.0ports.Theseports

supportdatatransferratesof3.0Gb/s.TheCPMconnectstwoSATAports(0and1)foruse

withtheoptional1.8inchmicroSATASSDdrivesthatcanbeinstalledinanoptionalRadisys

DSSDMXMmodule.

Low Pin Count (LPC) Bridge

TheLowPinCount(LPC)bridgeofthePCHprovidesread/writecyclesformemory,I/O,DMA,

andBussMasterdevices.ThePCHimplementstheLPCInterfaceSpecification,revision1.1.

ThedevicescontactedoverthisLPCbridgeincludetheIPMIcontroller,theport80debug

header,theCPUcomplexFPGA,andtheTPM.

Serial Peripheral Interface (SPI)

ThePCHprovidesa4‐pinSPIinterfaceforconnectingtoandcontrollingtheBIOSandME

FlashdevicesontheCPM.Therearetwo64MBFlashdevicesconnectedtotheSPIbusthat

storeBIOSbootandre dundantBIOSbootcode.Another64MBFlashdevicecontains

redundantMEfirmwareimages.OnCPMpower‐up,theprimaryBIOSFlashdeviceisselected

andused.IfacorruptBIOSisdetectedduringoperation,theIPMCforcesarebootandloads

theredundantBIOSFlashimage.

TheSPIbusallowsthePCHtoreadandalsoprogramtheprimaryandredundantBIOSboot

FlashdevicesaswellastheMEfirmwareFlashdevice.Controllingsoftwareaswellason‐

boardjumpersprovideFlashdevicewriteprotection.

Real-Time Clock (RTC)

ThePCHimplementstheCPMreal‐timeclock(RTC).Ratherthanabatterybackup,theCPM

usesa1F“SuperCapacitor”tostoreandsupplytheminimum2VbackupRT Cpower.Asa

consequence,RT Cpowerisavailableforatleasttwohoursafterasystempowerloss.

TheRTCisderived

froma32.768KHzcrystalwiththefollowingspecifications:

• Frequencytolerance@25°C:±20ppm

• Frequencystability:maximumof‐0.04ppm/(°C)

•AgingF/f(firstyear@25°C):±3ppm

•±20ppmfrom0‐55°Candaging1ppm/year

TheRT C’scapacitor‐backedRAMsupportstwo8‐byterangesthatcanbelockedduringpower

loss(i.e.,noread/write)whenthelockingbitsareset.Oncearange

islocked,therangecan

beunlockedonlyabyapowergoodreset.