User manual

Chapter 2
Installation
2-3
T able 2.A
SW1 Set of Switches
Switches 1-6 Switch 7 Switch 8
DH+ station number for channels
1A and 0 (see Table 2.B)
Unused (off) Memory protect.
If on, RAM memory protect is enabled.
T able 2.B
Station Numbers SW1 (Switches 1-6)
Station
N mber
LSD MSD
Number
(Octal)
1
2 3 4 5 6
0 on on on on on on
1 off on on on on on
2 on off on on on on
3 off off on on on on
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
77 off off off off off off
Table 2.C and Table 2.D describe the switch settings for SW2.
T able 2.C
SW2 Set of Switches
Switches 1-3 Switch 4 Switch 5 Switch 6 Switch 7 Switch 8
A16 address range of the
configuration registers.
See Table 2.D.
If on, the processor functions as the VMEbus
system controller, and no other VME cards
should attempt to be the system controller.
Important: The PLC-5/VME processor must
be in the left-most slot of the VME chassis.
See page 3-1 for a description of the
system controller.
Unused
(off)
VMEbus request level.
If switch 4 is OFF, switch 6 on defines
the bus request level as 3. If switch 6
is OFF, the bus request level is 1.
If switch 4 is ON, the bus request
level is 3 independent of the setting
of switch 6.
Unused
(off)
1
Unused
(off)
Important: Switch 6 is meaningful only if switch 4 is off.
1
SW2, position 7, now controls whether the PLC-5 processor makes a VME self-reference in its POST test. If you set SW2, position 7 to OFF (up position), then the VME will make
self-references as it did before series C, revision K. If you set SW2, position 7 to ON (down position), then the POST test will skip all VME self-references, causing the following ef fects:
– The PLC-5 processor cannot test its bus-master hardware.
– The PLC-5 processor cannot determine its own unique logical address and assumes its ULA is F0H regardless of how you set SW2, positions 1–3.
– The VME status file ULA field (word 1, bits 3-15) will always contain 000, regardless of how you set SW2, positions 1–3.