Technical information

Vee
All
9
8
20
CS
10
21
V
pp
Vee
18
PD/PGM
4.7K
R11
t
~33
ROM*
PIN 9 OF 221
Vee
12
11
11
20
CS
13
21
V
pp
18
PD/PGM
234
Note:
Version
"A" Board:
- ROM* sourced at
-221. pin 9
-
RAM* sourced at -221, pin 7
- -23 not used.
To Pin 3
of 235
-271 (4K)
1 14
0- --0
<r----o---o---- A6
0- -0
7 8
To Pin 13
of all RAM's
RAM*
0- --0
To Pin 15 <r----o---o---- GND
of~67
0- --0
Version "0" Board:
- ROM* and RAM* sourced at-23
as shown on the Master Schematic.
-23 is used.
Note 2: A 14-pin Jumper Header is used at-271
on Version "A" Boards only.
FIGURE 23. Spare Gate Usage on Version "A" or "0" Boards
101