Catalog No 26-2103
Ita!! I aeK A DIVISION OF TANDY CORPORATION One Tandy Center Fort Worth, Texas 76102
SECOND EDITION SECOND PRINTING - 1982 All rights reserved. Reproduction or use, without express permission, of editorial or pictorial content. in any manner. is prohibited. No patent liability is assumed with respect to the use of the information contained herein. Wh iie every precaution has been taken in the preparation of this book. the publisher assumes no responsibility for errors or omissions. Neither is any liability assumed for damages resulting from the use of the information contained herein.
Preface We'd like to share a couple of important points before you get into this book. 1. This Book was written for the technical person, by a technical person. It was not written to educate the average owner of a TRS-80 Micro-computer. If you do not know what Hex means. .. or how a NOR gate differs from a NAND gate ... you are not prepared to repair your Computer. (You need some solid digital logic training; and this Book won't give it to you.
Table of Contents Page Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 System Block Diagram Description 9 The Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 12 THEORY OF OPERATION 14 CPU Address Lines ;' 16 CPU Data Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 17 CPU Control Group 18 System RAM 24 Video Divider Chain 28 Video RAMs. . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction Armed with only a Schematic, attacking a TRS-80 Computer may at first seem to be the ultimate exercise in futility. But that's where we come in. This book has been written with those kinds of feelings in mind (matter of fact, the writer went through many of the feelings of trepidation as he was first asked to trouble-shoot and repair an early TRS-80 ...). You may know what "CPU" stands for. You may even have some knowledge of how a microprocessor system works.
System Block Diagram The 80 integrated circuits contained in the TRS80 can be broken down into about 10 major sections. Figure 1 shows these sections as they relate to other sections. The heart of the system is definitely the CPU (Central Processing Unit). You might consider the CPU as being a very dumb calculator circuit. It may be dumb, but it's a fast dummy. Most of the leads on the CPU Cire data linesand address lines.
OV OUT 1---4 t> TO ALL SECTIONS 12V TAPE INTERFACE t> TO RAM 5V IN ---{> DATA IN/OUT DATA IN/OUT DATA OUT RAM KEYBOARD cs l ... v TAPE RECORDER/ PLAYER 1',,.--- DATA IN/OUT EN cs VIDEO RAM VIDEO PROCESSING VIDEO 1+ TERMINAL VRAM .ECT ISTER .OCK VIDEO DIVIDER CHAIN DOT CLOCK FIGURE 1.
RAM The next major section in Figure 1 is the RAM (Random Access Memory). This memory is where the CPU may place data it doesn't need until later. The RAM is also the place where the programs are kept. If you tell the computer to count to 10,000, then the CPU stores your instructions in the RAM. If you tell the Computer to do it now, here is what happens: The CPU tells the ROM someone wants in. The ROM tells the CPU to go to the Keyboard and find out who. The CPU finds out, tells the ROM that it's The boss.
It acts somewhat like a multipole, multiposition switch. When the Video Divider Chain is in control, the MUX is switched so that only addresses from the divider chain are directed to the Video RAM. The CPU may need to read or write data into the Video RAM. If so, the MUX is switched so that the CPU has control over Video RAM's address. After the CPU is finished, the addressing task is reassigned to the Divider Chain.
HEX ADDRESS DESCRIPTION OF CONTENTS/USAGE 0000 To 0FFF Level I ROMS 1000 To 37FF Not used 3800 To 38FF Keyboard 3900 To Not used 3BFF 3C00 To 3FFF Video Display 4000 To 41 FF RAM Used by BASIC LEVEL 1 4200 To 4FFF 5000 To 5FFF 6000 To 7FFF 4K RAM Useable RAM starts here-.-J 1 RAM 8K RAM 1 16K RAM RAM 8000 To FFFF Not used NOTE: Map not drawn to scale. FIGURE 2.
heory f peration System Clock The System Clock is shown on Sheet 2 of the fold-out Schematics at the back of this book. Y1 is a 10.6445 MHz, fundamental-cut crystal. It is in a series resonant circuit consisting of two inverters. Z42, pins 1 and 2. and 3 and 4, form two inverting amplifiers. Feedback between the inverters is supplied by C43, a 47 pF capacitor. R46 and R52 force the inverters used in the oscillator to operate in their linear region.
its reset state, and will start executing instructions from the ROM, starting at address 0000. Notice that the only time pin 26 of the CPU is ever low is a few milliseconds after power is applied. Once C42 charges up past the logical "1" level, pin 26 stays high until C42 is discharged when power is removed. Why is 253, a NAND gate, drawn as an OR gate? Notice that pin 11 is high only when either of the inputs are low.
a wait status until it goes back high. Once high, the CPU continues with the operation. For example: Assume you have a memory system that takes 100 microseconds before addressed data can be guaranteed to be present at the output. When the memory logic sees that the CPU wants data, it will make the WAIT line low. After 100 microseconds, the logic will make the WAIT pin high, and the CPU will input the data. The INT (Interrupt Request) is at pin 16 of Z40.
CPU Data Bus The data bus is buffered like the address bus, except for one area. Notice that there are only eight data lines at the CPU, labeled D0 through D7. But there at 16 buffers. Remember that the CPU must receive data as well as send data. The address lines are strictly CPU outputs. while the data lines are inputs and outputs. Therefore. there must be two sets of buffers for the data line. One set handles CPU output data while the other set takes care of the CPU input data.
CPU Control Group we now know how the CPU accesses the address bus. We know the data bus is used to gather data into the CPU or pass data out of the CPU. What we do not know at this point is how the CPU stores data in a memory or how it tells the ROM or RAM that it is ready to receive data. The CPU control group performs this task. These signals are: RD, WR, OUT and IN. Pin 1 of Z23 is tied to the WR output on the CPU. Pin 2 of Z23 is tied to IORO (Input! Output Request) which is pin 20 of the CPU.
Address Select). A15 is the most significant bit of the address bus. Let's combine the six high order bits and add a couple more, so that we have two hex digits: Address Decoder As shown in Figure 2, the TRS-SO is memory mapped. Therefore, the address 01AC (in HEX) is in the ROM part of the map. Address 3S0A is in the Keyboard area and 3CAA accesses the Video Display RAMs.
N o Al0 11 4 All KYBD* 6 8 .-----[> VID* +5V Z52 R48 4.7K Z52 f'- - - - - - - - - - - - - - - - - - - - [ > ROM A* 12 RD* ~L +5V 16 A12 A13 o: 131A t> . 3 • t> : IB Z21 Cl 151 C2 62 61 11 11 I'... I I I 2 -_.""'" 6 3 : 5 4 : 4 5 : TR62 4.7K 15 __ - I I 13 I 12 ___ I _,__ f1' 4 I>-- ~...------~I - ~ RAS.~6 A15 ROM B* +5V I ---<0!! 8 10 -0 : 6- l----~·'I MEM* 9 :-----: 12 7 4.7K 7 10~~.1 74LS156 A14 r-~~"T 4 7K 1 .
Now, look at Fig~re 3 and you'll see that bits A12, A13 and A14 are connected to Z21, a dual, 2-input to 4-line decoder/demultiplexer. The C1 and C2 inputs are connected in such a way as to make Z21 into a 3-input to 8-line decoder. The G1 and G2 inputs to Z21 are chip enables. As shown, when these inputs are at a logical 0, Z21 is active. When high, Z21 is disabled and none of its eight outputs are low. The G-enables are controlled by OR gate Z73, pins 4, 5 and 6.
find MEM* on the big Schematic, you will notice it controls the ROM!RAM buffers. The outputs of the buffers are tied to the data bus. We now get ROM data onto the data bus. Has it got a way to get to the CPU? Yes, it does. Reme.mber that RD is low because the CPU is in a Memory Read cycle. Since this is so, DBIN* is low and OBOUT* is high. The low at OBIN* enables the CPU's input data buffers and ROM data is available for the CPU. Keyboard Decoding The Keyboard is located from address 3800 to 38FF.
Notice on Z3 that we can program the system for 8K of RAM by leaving the shorting bar intact at pins 3 and 14, and at the 2 and 15 position. Not only would a 4000 address cause RAM*, but a 5000 address would also enable RAM*. If we had 12K of RAM, we would leave pins 4 and 13 shorted. For 16K, we short all pins we have mentioned; plus pins 5 and 12. RAM* would now be active from addresses 4000 to 7FFF. As you can see from the RAM discussion, we'll be shorting certain outputs of Z21 together.
System RAM According to the Block Diagram, System RAM is tied in parallel with the data bus and address bus just like ROM and the Keyboard. The data input and output for RAM is straightforward enough; MEM* controls the buffers. But the addressing scheme appears all screwed up. How can the CPU address a minimum of 4K of RAM using only seven address inputs? The answer to that very good question is - multiplexing. The address from the CPU is multiplexed into the RAM in two 7-bit parts.
LINE ~69 A ClK B MREO it-40 PIN 19 C WR it-40 PI N 22 D MREO it-74 PIN 3 E NEXT ~69 PIN 5 F OMUX it-69 PIN 9 H OCAS it-7f/J PIN 6 J RAS* it-72 PIN 5 K MUX ~72 PIN 3 l CAS* it-72 PIN 9 PIN 3 FIGURE 4.
RAM Addressing In about the middle of Sheet 1, on the left side of the RAM array, multiplexers Z35 and Z51 are shown. On the left side of Z35, we find the area where four address lines are coming in. One brace of four is labeled "0" and the other is labeled "1". Z51 is configured the same way except there are only three lines per brace. The tells us that when the select pin is low, the multiplexer will be outputting data associated with these input lines. The "1" tells us the opposite is true.
RAS* is generated by the CPU at pin 19 (MREQ)' Whenever MREQ goes low, RAS* goes low; and the RAMs will load the lower order address into the row section. The CPU may be looking at system ROM when MREQ goes low, but RAM will still receive RAS* and thus be "refreshed. " Normally, you would not be too concerned about this aspect of the RAMs. But you need to be aware of the differences between a static RAM and a dynamic RAM. Remember: Dynamic RAM must be periodically addressed to enable it to retain data.
a reference frequency in a 64 character format. The D flip-flop supplies the counter with the reference frequency in a 32 character format. Video Divider Chain The Video Divider Chain supplies the Video RAMs with addresses in a logical order for Video Processing. This chain also supplies the horizontal and vertical sync timing pulses so that the Video Processor can build the composite waveform for the display.
and "D" version P.C. Boards with Z58, pins 6 and 7 simply tied to ground. Z58. pin 12, is labeled DOT 1. Z58, pin 9, is labeled DOT 2. DOTs 1 and 2 are "NAND-ed" by Z24; and the resulting output is shown in Figure 5 at line G. This signal is called "LATCH" and is used in video processing. Z43, pins 6 and 10 are tied together and are connected to Z58, pin 8. The rE?sulting output at Z43, pins 7 and 9. will therefore be the same signal. Pin 9, labeled CHAIN is the divider chain's main source.
)" "ZERO" "ZERO" 1 1 r-- L..-- LJ LJ LJ LJ "Z ER0" "ZERO" + • 1.. . . _ ---' 11- 11... --------' ---' FIGURE 5. Input Conditioning Wavefonn The signals that changed are very important to the Video Processor section. The first, LATCH, is used to delay a character between RAM and the character generator. The second signal. C1, determines if the RAM has 10'24 or 512 useable addresses.
Upon the next negative excursion of the clock pulse, outputs would look as follows: Divider Chain The Divider Chain circuit (Z65, Z50, Z12 and Z32) consists of four-bit ripple counters. They hve a maximum count of 16, but external circuitry may modify this maximum. Output Output Output Output o A B C 0 1 1 1 Figure 6 shows a simplified block diagram of the counter chain. Refer to Figure 6 and to Sheet 2 during our discussion of the counter chain. which is equal to 14.
sider Z12 as a divide-by-12 counter instead of a divide by 13 counter! If 15.840 kHz is applied to Z12, pin 14, then the output at pin 11 will be 1.32 kHz. The next divider is part of Z65. On Sheet 2, follow pin 11 of Z12 up to Z65, pin 14. The output is at pin 12. Follow it back down to Z32, pin 14. This part of Z65 divides the 1.32 kHz input by two: therefore, the frequency at pin 14 of Z32 will be 660.0 Hz. Z32 is the last counter in the chain. It divides the 660 Hz input by 11, producing 60 Hz.
generated back in the address decoding discussion? We said VID* will select the Video RAMs. Notice that pin 1 of the 3 multiplexers is tied to VID*. When the CPU wants control over the Video RAM, the address decoder recognizes the Video RAM address and causes VID* to go low. When VID* is low, the multiplexer switches the "0" inputs over to the multiplexer outputs. The counter chain addresses are switched out of the circuit, and the CPU has control over Video RAM.
Video RAMs The Video RAMs are static and do not need refreshing. The data bus is wired in the same way as system RAMs, but with a different enable signal. One interesting point to note: There are seven RAMs. Six are used for ASCII storage, and the seventh is used as a graphic/alphanumeric definition bit. There are eight data lines. Notice the line labeled Bit 6. It is sourced by NOR gate 230 at pin 13. If Bit 5 (262, pin 12) and Bit 7 (263, pin 12) are low, then Bit 6 will be high.
At the same time 228 stored the ASCII word, the Divider Chain changed Video RAM addresses. The RAM is now "looking" for the next ASCII word. It has exactly six dot times (about 560 nanoseconds in 64 character format) to find it before the Latch is commanded to store the next word. 227 is a smaller latch that operates exactly the same as 228. But instead of ASCII, it handles the graphic bit and blanking data. Pin 4 is tied to the inverted output bit from 263, the graphic RAM.
Character Generator Each character consists of a dot matrix. The matrix is five dots wide by seven dots deep. There is one dot between any two adjacent characters that is never turned on. We have five dots, a space, five more dots, a space, etc. Vertical spacing between adjacent data is determined by the frequency of the dot clock. (In the TRS80, the dot clock signal is labeled SH IFT.) The dot clock is oscillator frequency, in 64 character format, and 1/2 oscillator frequency, in 32 character format.
It I LEFT L 8 L 4 o 0 o 1 I I I RIGHT UPPER 4 T SCAN LINES ~ MIDDLE DIRECTION o OF SCAN LOWER 1 CHARACTER POSITION ;;;;;: 6 GRAPHIC CELLS FIGURE 7. Rectangle and Graphic Cells Z8 is the Graphics Generator. Actually, Z8 does not generate anything. Rather, it steers the ASCII addresses around to simulate a graphics generator. The input to Z8 is ASCII from Data Latch Z28, and the higher order line address from Z12, L4 and L8. L4 and L8 can represent any four numbers from 0 to 3.
Alphanumeric/Graphic Shift Register Z10 is the Alphanumeric Shift Register and Z11 is the Graphic Shift Register. Both devices receive parallel data from their respective generators. The parallel dot data is loaded into the registers and the dot clock (labeled SH IFT) will march the dots out, one behind the other, to the video mixer. We will discuss the Alphanumeric Shift Register first. There are a few restrictions when the Alphanumeric Shift Register should serialize dot data and when it shouldn't.
Delay blank (DLY BLANK) is tied to Z26, pins 1 and 2. When high, this input tells Z26 that the electron beam is indeed in the video portion of the screen. Once all conditions are met and LATCH goes low, Z26 will go low. Just like Z10, Z11 will load dot data; and when pin 15 goes back high, the shift process will start. The six graphic dots are shifted out of pin 13. Notice pin 9 of Z11 is pulled up by R40. Likewise, pins 3, 2, 1 and 6 are tied to ground. But pin 14 is used this time.
Horizontal and Vertical Mixing Once the two sync pu Ises are phase-sh ifted and pulse-shaped, NAND gate Z5 is used to mix the two signals together and serrate the vertical interval. Figure 8 shows idealized waveforms around Z5. At Line A, the horizontal pulses are shown. The source for this output is Z6, pin 8. At Line B, the vertical pulse is shown coming from Z57, pin 8. Z5, pins 1 and 2 are tied to the waveforms shown at Lines A and B, and the resulting NANDed output is shown on Line C.
oJ « I- z ~ cr: 0 > 0 cr: :r (.) z > en oJ « (.) j::: 0 w w X :E ~F '"z w Z ..J '"z '"z ;;: ;;: '"N N N co (.) « .... U'l ;;: U'l rz '"z '"z ;;: c. ;;: U'l U'l N N N 0 W U.
5.0 VOLTS T Video Mixing The Video Mixing circuitry generates the composite video signal for the display. The video mixer accepts alphanumeric or graphics dot data from the shift register, level-shifts it, and places it atop the composite syncs. The composite waveform is then buffered to drive a 75 ohm impedance and is sent, via cable, to the Video Display. Dot data from Shift Register Z10 or Z11 is applied to Z30, pin 3 or pin 2. You should never see both pin 3 and pin 2 active at the same time.
WHITE LEVEL T '.'VOLTS VIDEO // TOP OF SCREEN \ te VERTICAL SYNC -i lOVOLTsrIL-f ! 'V 0.4 VOLTS 4 r- SCAN LINE HORIZONTAL SYNC BOTTOM OF SCREEN FIGURE 9B.
Keyboard Input and Output Port The TRS-80 Keyboard consists of 53 single-pole, single-throw normally open keys molded in a plastic base. The base is mounted, together with four ICs and associated resistors, to the keyboard PCB. As you can see from the Schematic, this Keyboard does not output ASCII. It is scanned, like calculator-type keyboards. Each key represents a switch across a matrix node. When closed, the switch will short out a horizontal line to a vertical line.
port), Z25, pin 6 will output a low generating INSIG* because IN* and FF* are low. IN* and OUT* should never be active (low) at the same time. Thus, I NSIG* and OUTSIG* should never be active (low) at the same time. ing current to flow through relay K 1's coil. K 1's contacts close, shorting out pins 1 and 3 of J3. These two pins are associated with the remote jack at the Recorder. The Recorder's motor will then turn on. OUTSIG* Notice diode CR3 and Zeners CR9 and CR10.
Cassette Audio Output After the motor is turned on, the CPU may output data for storage on tape. All data timing for this output function is software controlled. Z59 is used to store data from the CPU and it "builds" the output waveform using CPU data. CPU data, under software control, is applied to latch Z59 on pins 4 and 5. Output pins 2 and 6 are connected to a resistor network consisting of R53 through R56.
"1"= IF PULSE PRESENT "0"= IF PULSE NOT PRESENT ~T1_+ T3~T1---1 n n . Ur-------...... Ur----- ---- --------'nU 0.85 V 0.46 V ---0.0 V 1+----- 1 ms---1 NOTE: PULSE WIDTH NOT DRAWN TO SCALE .....- - - - - BIT TIME 2ms-------_.1 = FIGURE 10.
Cassette Audio Input If the Recorder could faithfully give back what was sent to it, we could eliminate a quad operational amplifier and a handful of passive components. But, it doesn't; so Z4 stays in. Matter of fact. the Recorder adds stuff to the signal. Motor noise and 60 cycle hum complicate signal processing considerably. Upon a CLOAD instruction from the CPU. the Recorder motor turns on and cassette audio is applied to pin 4 of J3.
4.0 V 1r--- BIT TIME 2mSEC _I ~ LINE A Z4 PIN 5 2.0 V ~ FILTERED AUDIO BASE LINE OV B CR4 CATHODE NOTE: AMPLITUDE WILL VARY DEPENDING ON RECORDER VOLUME LEVEL. FULL·WAVE RECTIFIED AUDIO 2.0 V OV C Z4 PIN 9 INVERTED I AMPLIFIED AUDIO 2.4 V OV D CR7 CATHODE 1.GV FILTERED AUDIO OV E Z4 PIN 10 4.4V OV 1.1 W w w w FIGURE 11.
INSIG* Exactly how the CPU turns a string of ones and zeroes into the text of a BASIC program would interest only the hardcore software person. The amount of hardware used in the TRS-80 to get cassette data to the CPU is minimal. Only the hardware will be discussed. Z25, pin 4, is tied to IN*. This signal will go low when the CPU wants to input data from a port. Port Addressing has already been discussed. A low at pin 4 of Z25 and a low at address decoder Z36, pin 3, will cause a jaw at Z25, pin 6, INSIG*.
BIT TIME 1 BIT TIME 2 BIT TIME 3 1:--. - . 0.----1-11-. -"O..---t-I-·-"''' LINE A 224 PIN 9 B INSIG' c OUTSIG' D 224 PIN 8 u u u u --U u u BIT TIME 4 1_·-"0"---1 u u u u u NOTE: PULSE WIDTH NOT DRAWN TO SCALE FIGURE 12.
+ 12 V Power Supply System Power Supply The TRS-80 needs three voltage levels: +12 volts at about 350 milliamps; +5 volts at about 1.2 amps; and -5 volts at 1 milliamp. The +12 and -5 volts are needed by system RAM and everything needs +5 volts. The +12 volt and +5 volt supplies are regulated and current-protected against shorts. The -5 volts supply is not as critical as the other two supplies, and it uses a single zener diode for regulation.
V+ Vc ----------- t----~ OP 11 ---------, I I AMP POWER I I _---~10 Va 1 7.15 VOLT Za OPAMP POWER _ _ _ _ _ _ ..J L __ V- Vref + COMP FIGURE 13. Block Diagram of 723 Regulator Z2 The transistor labeled Ob in Figure 13, is used to protect power transistor 06 against over-current damage. If R18 drops sufficient voltage to cause the resistor node at Z2, pin 2, to reach 12.6 volts, Ob will take command of Oa. As Ob the input voltage level because of R16.
+5 Volt Supply The 5 volt power supply also uses a 723 regulator. Due to the current and voltage requirements, more components were stuck around the regu lator for support. But the basic circu it operates the same. Figure 13 will also be used in this circu it. For the 5 volt supply, the AC adapter supplies about 17 volts AC at Jl, pins 1 and 3. Full-wave rectifier CR8, rectifies the AC. When S1 is closed, about 7 VDC is passed through the switch contacts and is filtered by C9.
Level II ROMs One of the most fascinating aspects of a computer is its versatility. It can do almost anyth ing; all it needs to know is how. With a single ROM change, the TRS-80 can speak in any higher level language we might care to use. In Level I we had just enough mathematical and symbolic capabilities to inspire bigger and better things. The difference between a Level I TRS-80 and a Level II TRS-80 is inspiration and a bigger ROM. Level I uses 4K of ROM. In Level II, the system uses 12K of ROM.
djustments & Troubleshooting 57
Disassembly 1. Position the Computer, keyboard down, on a soft surface. 2. Remove six screws from the bottom of the Case. Keep track of the different lengths so you are sure to replace them in the correct holes. 3. Turn the Computer right side up and carefully separate the case halves. NOTE: There are two different types of LED mounting A. Keyboard PCBs which are double-sided, with plated holes use an LED mounted into the top half of the Case. Long wires connect the Keyboard PCB and the LED.
CASE, TOP ~:'-:r---T i ~ ~ CASE. BOTTOM - . / .1'~/J I . SCREW 6-32 x 1'1."(4.5cml ~ A,~ n t1_------ SCREW 6. 32 x2"(5cml = ... LED. SOCKET AND RETAINER RING SCREW 6-32 X1'1."(4.5cml SCREW,THREAD FORMING 1"(2.5cml FIGURE 14.
Power Supply Checks And Adjustments Once the PCB's have been removed from the Case and are resting on the test bench, connect the Power and Video DIN plugs. CAUTION The CPU Board is now "upside down" in reference to its normal position in the case. Be sure you connect the Power DI N plug to the Power jack (J 1) and not to the Cassette jack (J3). The Power jack is the one closest to the Power switch. Turn on power to the CPU Board and the Display.
J3 (TAPE) J2 (VIDEO) COMMON R10 ;5 / / / R18 (+ 12 VDC) / \ RESET CR2 FIGURE 2. LOGIC BOARD FIGURE 15.
Section Isolation Usually, problems or complaints are directed to a certain function. For example: C LOAD is fine, but when LiSTing the program, half of the listing is a screen full of junk. Since part of the LiSTing is correct, we can assume the audio processing circuitry works. You might suspect: 1. A problem with tape data or, 2. a' RAM error is screwing up the data input. You might listen to the tape's audio for voids, or attempt to load a test program and exercise the RAM's.
DISASSEMBLE UNIT GARBAGE ON SCREEN AT POWER ON f---------,~ CONNECT VIDEO AND POWEr DIN PLUGS PRESS ON POWER SWITCH 1 2 4 INTERCONNECT CABLE SOLDER BALL SHORT TURN OFF POWER WAIT 10 SECONDS TURN ON POWER 5 7 6 YES TURN OFF POWER S REMOVE DIP SHUNT AT 271. TURN ON POWER 10 9 11 14 15 16 TURN OFF POWER REMOVE ROMS TURN ON POWER 1S 17 19 SCREEN SHOWS SOME@9's FIGURE 16.
a screen full of @9's. The Display should be in 64 character format at this time. The Display will flicker as VI D* continually accesses the video ROM's. logical 1. It is held high by resistor R50. Another example is the logical 0 at pins 6 and 7 of Z56, the CPU clock divider. Z42, pin 8, is always low unless resistor R67 is grounded. If you get @9's on the screen, you probably have a ROM error. If no @9's or partial @9's are visible, you could have video chain or video RAM problems.
CPU ClK SOURCE NO BAD NO SHORT? NO CHECK SWITCH S·2 AND RESET lOGIC SOLDER NO POWER·UP CLEAR lOGIC DEFECTIVE YES OPEN PCB ETCH? MAY NOT BE CPU PROBLEM···· SECTION ISOLATE YES REPLACE 240 (CPU) CAS/RAS lOGIC FIGURE 17.
trouble-prone just because it's in a socket and is easily replaced. The flowchart, shown in Figure 17 will help in CPU troubleshooting. The primary objective of this chart is to help you quickly find a signal that should be active but isn't. The main flow of the chart is on the left side of the Figure. Here, you are checking for activity on address and data lines. With no activity on the address lines, you are immediately branched off to the CPU's support group to find out why.
in a conductive tube or in conductive foam. DO NOT USE STYROFOAM! Unless specially treated, styrofoam eats MOS devices like candy. It can generate tremendous static charges. Do not use cellophane tape to hold RAM's in sets of eight. The process of removing tape from the roll will act as a handheld static generator. Failure of address decoding will usually be associated with one of the higher order address lines.
4. Unsolder the contacts from the PCB. Be sure that the contact ends (protruding through the Board) are actually free. This is important when you are working on double-sided Boards. 5. Note the position of both types of contacts. The fingered contact is usually on the right side, with the keyboard oriented in a normal position. 6. Using a pair of strong needle-nosed pliers, pull both contacts out of the plastic base.
SIGNAL NAME SIGNAL SOURCE SIGNAL FREQUENCY DIVISION RATIO COMMENTS Z32 Pin 11 60.00 Hz 177.3517 X 103 R8 R4 R2 R1 Z32 Pin Z32 Pin Z32 Pin Z65Pin 60.00 180.0 360.0 660.0 Hz Hz Hz Hz 177.3517 59.11722 29.55861 16.12288 X X X X 103 103 103 103 Character Character Character Character l8 l4 l2 l1 Z12Pin11 Z12Pin8 Z12Pin9 Z12Pin 12 1.319 kHz 2.639 kHz 3.959 kHz 7.917kHz 8.067550 4.032247 2.687825 1.
Video RAM If you suspect Video RAM problems, you should try a SCOATS loading. SCOATS will be most helpfu I in rooting out bit-error in the RAM's. If the test generates large amounts of bit-errors, you should suspect either the Divider Chain or the Video RAM addressing multiplexer. Multiple "Ready", If>" and characters all point to RAM addressing errors. Normally, addressing errors occur when there is a short or open between the multiplexer and the RAMs.
ting, maybe Z30, pin 2 is being held high for some reason. Maybe Z26, pins 8 and 6 are both high. What could cause this? Is Z27 working? Is flip-flop Z7 always reset? Maybe LATCH is not active. If so, both Z7 and Z27 will not operate. Sometimes it helps in video troubleshooting to force a screen completely full of data. Pull BASIC ROM(s). The CPU will try to go into an @9 state. If nothing else, you will now have an easily recognizable scope pattern you can trace.
Address Decoder Expanded Discussion Since the Address Decoder is made up of gates, it is extremely easy to fix once you find the problem. The hard part is knowing when to suspect a fault with the decoder section. Section Isolation demands that the Address Decoder be functional, at least partially. Unfortunately, there is no "cut and try" method to determine if this section is working correctly.
Cassette Problems Most of the difficulties you'll find in this section will be related to no recorder motor control. Usually, Kl (a reed relay) will have gone bad because of overwork. Relay damage is particularly susceptible in Level II units. That buzz you hear every time you power up a Level II unit is the relay going bananas during the CPU's lengthy initialization routine. The power-up routine and the added recorder usage, because of more efficient file storage routines, make K1 earn its living.
A RAM bit error usually shows up in CLOAO when you find part of the loaded program correct and the other part garbage. Use SCQATS to dig out this type of error or, play the RAM swap game until you find the defective part. A CPU problem is usually more common than a ROM problem in a CSA VE condition. This is true simply because you will be more concerned in getting a "Ready" on the screen than you are in seeing if the unit will CLOAO.
stall each RAM until you find one that crashes the power supply. Remove the bad RAM and continue to check the rest of them. There may be more than one shorted device. A short on the +5 volt bus can be a real headache. Unless you can see the short, you will have to cut runs to Section Isolate. Once you isolate the shorted section, you will probably still have to make other cuts to get down to the short. Do not forget to repair your cuts. And remember, these runs must carry considerable current.
Horizontal and Vertical Adjustment After components in the Sync Generator are replaced or after other repair work, the horizontal and vertical centering shou Id be confirmed. Enter the following sample program: 1.0 CLS 2.0 FOR X=.0 TO 127 3.0 SET ( X , .0 ) 4.0 NEXT X 5.0 FOR Y=.0 TO 47 6.0 SET ( .0 , Y ) 7.0 NEXT Y 8.0 FOR X = 62 TO 65 9.0 SET (X,23) SET (X,47) : SET(127,X) : SET (X,24) 1.0.0 NEXT X 11.0 GO TO 11.0 You can load th is program on a tape several times (for easy use).
Look on the etch side of the Board under the RAMs. You might find an installation error. A socket lead is easily bent. Maybe the lead was folded under the socket body and not soldered in a hole. There may be just enough pressure on the lead and the pad to allow spastic operation. Look for a smooth coating of solder instead of the pointed cone you would expect if a wire or lead was protruding through the Board. Don't limit your visual inspection to socketed parts only.
The Gate With The Static Output How many times have you come across a logic element that has data screaming into it and an output that just sits there? Probably too many times, especially in a major area like the address decoder where you really don't need that kind of "hassle". Normally, you attach a scope to the gate inputs and see if output conditions are ever met. If you have two gate inputs and two scope channels, you'll do OK. But, you can get gray hair trying to analyze an 8-input NAND gate that way.
The solder splash short is probably the most common. This short develops due to excess solder and/or careless repair techniques. A solder bridge can develop between two pins on an integrated circuit during installation because of excess solder or too large a soldering iron tip. The true solder splash results when a soldering iron loses a bubble of solder, and the TRS-80 is on the receiving end. Usually, a splash is easily detected. They are big and cold-soldered to several runs.
The counters used in the divider chain are 74LS93's. This family of TTL ripple-counters sometimes shows a multilevel high on the data outputs. The wave shape appears to have one or more steps while the main pulse is high. This type of output is satisfactory if the steps do not fall below the 2.4 volt minimum logical high level. Usually, you will have a counter step of about half a volt or so, and the lowest step will never fall below 3.0 volts.
Bent Pins On socketed parts, it is easy to replace devices for troubleshooting. But, be careful that you do not cause more problems by getting in a hurry. On RAMs, it's extremely easy to bend an IC pin between the socket and the part. Suspect a bent pin if the part is hard to insert: and, upon more pressure, it suddenly snaps in. Make it part of your isolation routine to peek under the CPU chip and look for folded-under leads.
he utsid orld 83
-8 and he Outside World As you use your Computer more and more, you will begin to see more and more applications for it. There will come a time when you will want to do some tasks that can only be handled with external circuitry; or the BASIC language does not include such functions as "TU RNCP.X" (turn on coffee pot at time x). You know that a Computer should be able to do such things but you may not know how to go about designing a circuit to do it.
For example, if your coffee pot circuit is port addressed at FE Hex and 02 Hex will turn it on, an assembler routine that generates the machine code to load 02 into port FE is as follows: OUT 0FE,02H ; Turn on coffee pot In Level II language you could say: OUT 254, 2 (This is in BASIC and does the same thing.) The port instruction uses OUT* and IN* and the 8 lower order address lines. Should you memory-map or should you use ports? This is entirely up to you.
At line 600 in the program, the CPU will POKE data 2 (Hex (2) into memory-location -4092 (Hex 8FFF). In binary, 8FFF is 10001111 11111111. Memory Mapped External Device Figure 20 shows a logic diagram of a memorymapped coffee pot switch (of course it could be any other control switching circuit). It was drawn to illustrate a technique and should not be considered a final working design. The following assumed: software requirements were 1.
Vee 74lS367 ~ o D1D I • I TO com"o< > I W R * D - - - - - - - - - - - - - - - - - - - -q RD*D I K1 q Vee AO_ ~~~D 74LS30 A4 A5 Vee A6 < A7D----· 74LS02 A12 A13C:>- SFFF* q A14r':>------· AsD-----------A9D-------------A1OD-------A11~ Z3 74lS30 - A15 00 ...:J FIGURE 20.
remains the same but this time Z2D is active. Because, instead of WR* going low, RD* goes low and READ is generated. READ is inverted by Z5 and activates tri-state buffer Z4. Data present on the input is transferred to the output. If the relay is "on", Z4 will output to D1 a low; and if K1 is not on, a high will be outputed to D1. The program will take appropriate action depending on a status of D1 as line 900 shows. Notice that the hardware: 1.
Vee 74LS367 1 o 74LS04 f OUT*D-----------, -------0 } TO 00'' " '). K1 WRITE ---/ 74LS02 74LS74 READ IN' c:::>--------------I-I d A7D A6C A5:::::::::' >----------1 A4 A3C 74LS30 21 ):>------l FE' Vee Vce~ - A2- A1- ~ FIGURE 21.
Explanation of Expansion Port Signals The table on the facing page lists all the Expansion Port pin connections and signal names. Figure 22 shows the connection points as they exist on the back of the Logic PCB. The following detailed description of the various signals will aid you in understanding (and using) the Expansion Port. Address Output: There are 16 of these lines, labeled Ar/J thru A 15. Ar/J is the least significant bit, and A 15 is the most significant bit.
Pin Connections for ExpansionPort Edge Card SIGNAL NAME DESCRIPTION 1 RAS* Row Address Strobe Output for 16-Pin Dynamic Rams 2 SYSRES* System Reset Output, Low During Power Up Initialize or Reset Depressed Column Address Strobe Output for 16-Pin Dynamic Rams 3 CAS* 4 Address Output A10 5 Address Output A12 Address Output 6 A13 Address Output 7 A15 8 GND SiEial Ground A dress Output 9 All 10 A14 Address Output 11 A8 Address O~ut 12 Peripheral rite Strobe Output OUT* 13 Memory Write Strobe Output WR* 14 INTAK
Peripheral Read Strobe: IN * operates somewhat like RD*; except IN* is a port function. When IN* goes low, the CPU is looking for data on the address bus that comes from the port specified by the 8 lower order bits of the address bus (A0 thru A7l. The Z80 will address up to 256 input ports. Interrupt Input: INT*, when taken low, will force the CPU to a predetermined address in ROM. There are three modes of operation. In the first, this line is ignored.
s ist 93
a s List LEVEL I Logic Board Symbol Description Printed Circuit Board, Logic Part Number 1700069 CAPACITORS Cl C2 C3 C4 C5 C6 C7 C8 C9 Cl0 Cll C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 cnC23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 94 200 tIF, 16V, Electrolytic, Axial 10 tIF, 16V, Electrolytic, Radial 0.01 tIF, 10%, 25V, Disc 10 tIF. 16V, Electrolytic, Radial 10 tIF, 16V, Electrolytic, Radial 100 tIF, 16V, Electrolytic, Radial 0.
Symbol Description Part Number J2 J3 2100033 2100033 Connector, Socket, DIN, 5 Pin Connector, Socket, 0IN, 5 Pin RELAY K1 15V Relay 14500001 TRANSISTO RS 01 02 03 04 05 06 2N3904, NPN MPS3906, PNP TIP29, Driver 2N6594, Power MPS3906, PNP MJE34, Power 4822001 4822003 4820004 4824003 4822003 4824002 RESISTORS R1 R2 R3 R4 R5 R6 R7 R8 R9 Rl0 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 68 ohm, 1/2W, 5% 2.7 K, 1/4W, 5% 750 ohm, 1/4W, 5% 0.33 ohm, 2W, 5% 1K Trim Pot, 30% 1.2 K, 1/4W, 5% 1.
I Symbol Description Part Number Z10 SWITCHES Sl 82 4PDT Push DPDT Push 5102008 5102009 SINKS Sink Q4 Heatsink Sink Q6-14 Heatsink 16 Pin 16 Pin 16 Pin 16 Pin 16 Pin 16 Pin 16 Pin 16 Pin 16 Pin 24 Pin 24 Pin 40 Pin 16 Pin 5300003 5300002 I.C. Socket I. C. Socket I.C. Socket I.C. Socket I.C. Socket I. C. Socket I.C. Socket I.C. Socket I.C. Socket I.C. Socket I.e. Socket I.C. Socket I. C.
Symbol Description 4KRAMKit Part Number Integrated Circuits Z50 Z51 Z52 Z53 Z54 Z55 Z56 Z57 Z58 Z59 Z60 Z61 Z62 Z63 Z64 Z65 Z66 Z67 Z68 Z69 270 Z71 Z72 Z73 Z74 Z75 Z76 74LS93, Divide by 8 Binary Counter Selecto rIM uItiplexer 3102017 74LS157, Quad 2-Line to 1-Line Data Selector/Mu Itiplexer 3102020 74LS04, Hex Inverter 3102008 74LS132, Quad 2-lnput NAND Gate 3102018 74LS30, Triple 3-lnput NOR Gate 3102013 74LS367, TRI-STATE, Hex Buffer 3102024 74LS92, Divide by 6 Binary Counter Selector1M uItiplexer 310
R1 R2 R3 R4 R5 R6 R7 R8 R9 4.7 K, 1/4W, 5% 4.7 K, 1I4W, 5% 4.7 K, 1/4W, 5% 4.7 K, 1/4W, 5% 4.7 K, 1I4W, 5% 4.7 K, 1/4W, 5% 4.7 K, 1/4W, 5% 4.
h m ti s 99
chematics BASIC I ROMs Since the TRS-80 went into production, there have been three major PCB changes. These changes reflect different vendor's responses to system requirements as it pertains to the ROM (Read Only Memory). In the manufacturing process, certain vendors were able to supply ROMs to the factory at different times. Thus there are three major types of ROMs. There have been slight PCB Modifications as each ROM was used.
Vee 9 All 8 20 10 21 Vee 4.7K 18 CS Vpp PD/PGM t R11 ~33 ROM* PIN 9 OF 221 Vee 12 11 20 11 13 21 18 CS Vpp PD/PGM 234 Note: Version "A" Board: - ROM* sourced at -221. pin 9 - RAM* sourced at -221, pin 7 - -23 not used. Version "0" Board: - ROM* and RAM* sourced at-23 as shown on the Master Schematic. -23 is used.
National MM2316 ROMs The "D" version Board with National ROMs will usually have only two wire modifications or jumpers, directly under the ROM sockets. These jumpers will also have two etch cuts associated with them. Version "A" Boards using National ROMs may have more jumpers. This is because an "A" version Board may have been modified to use Intel EPROMs and then later remodified to accept the National ROMs. Be careful when identifying the different Board versions.
Motorola 7800 Series ROMs (Two Chip Set) Motorola was the next vendor to supply ROMs for the TRS-80. These ROMs may be identified by the part number 7807 for ROM A and 7804 for ROM B. These devices are used only on "0" version Boards and there are no PCB modifications. As with National ROMs, Motorola ROMs may be placed in either 233's or 234's socket. Motorola 7800 Series ROMs (Single Chip Set) The last ROM supplied to the factory was a single Motorola ROM.
BASIC II ROMs The early TRS-80s that have BASIC II ROMs are easily identified. There are no ROMs plugged into Z33 or Z34. Instead, there is a 4-conductor flat ribbon cable connecting the CPU Board to a small 4-chip ROM Board. This ROM Board is attached with double-sided tape to the etched side of the CPU Board. The three ROMs on this Board contain BASIC II. These ROMs may be supplied by various vendors. Figure 25 is the Schematic for Level II BASIC.
A7:--- - - --- ----:.5V '4 PIN '40--'-IA"-8'--~~~~~--' '-~~~~~~~~~=A6,-D' ~ HE~;ER ::~:)--i-~AC::9C-~~~~_11 ::: r-r~="':"':"':~"':"':"':==~A~31==~ 4 5 '33FOROR 2021 :, ,-__~~~_~A"-D 6 ,-~~~_=All1-D7 ADI ,-~~-"""--o 234 19 ,Al0 18' 9 10 160 'M06 15 IM05 J1 ~11 NOI 13 1 1 .....+-H1H-+--+--t-_t_--t--'-13 1 1 &-H1-++ --1-i--+--11-+---,,4 1 .-+-t-H!-+-+-t---=-:5 6 .-+-H-+-+--+-"-1 .1+++-HI~--'-i7 :MD3 0-;---, _ _ _ _ _ _ _ _ _ -1 .
-------1 A7 .--- 24 PIN DIP A6 2 A5 103 A41 4 A3 A? ...,6 A' I 7 AO I 8 MOO I HEADER FOR OR Z34 JI I I 'AIO 13~ ___ ..1 12 L __ 24 23 vee I A7 2 A6 3 A5 4 A4 A8 22 A7 es cs 5 A3 6 A2 21 20 19 AIO All 18 08 17 07 '6 06 '5 ZI 7 AI 8 AO 9 01 10 02 ~ ~ 21 A8 A9 18 MD7 17 ~ ' 16 ~ .MD6 MD5 15 ~ MD4 14 II I ' ~O , Z33 rr~o M02 24 23 22 05 14 03 04~ GND ROM A .
A7 A6 A5 A4 A3 A2 Al AO MDO MDl r--- I 24 24 PIN -v1 DIP 2 ~3 HEADER FOR ~4 Z330R 5 Z34 23~ A8 22- A9 21 I 20 I 19'""' ,Al0 ~6 ~7 ~8 I 18 17- MD7 ~9 16- MD6 15- MDS MD4 14'""' MD3 130-I Jl 10 ~-oll I ___ 12 L _ __ ..
® -@- SEE ,HEET 2 ROM ROM KEf IOARD 19 2MREQ MREQ *" '" 08~ (TO Z23, pins 4 and 12) 07 240 ~~___ M 'T6' " R9 r AI3 3 4 AI4 I I TO J AI5 5 GND 29 n$ I I R8 238 (pi ---------~~, QS : I lOOK I MPSS3906 I cia + 10,12,61 • CI4 I~t:~ O'~~eF¢ I ;;sv I~ )0 I 29 ; PL AC E::A 16-C19 IL MREQ 37 '39 CRI :~~/:3S 0'11~0~ (32 PLACES) C2 2,C2 3, C29, C31,C33,C3S-C38, C40,C41, C44-C56 (Revision D and after) RD'" 13 4--· 1.'74 )-'8~---'S::..j - Z3 Is 74LS011l b..;:6.......
["i30 - H1-----------. ISHTI) R52 910 R46 910 11~2 rkL~ TOGGLE +5V Dt-~42 3 4 10 10.6445 74LS04 CLK 2 L ... 13 I BIN A r!L 12 PRE CLR 9 '---'-" 0 1/2 Q F--I74 LS74 ,....lJ CLK op!L 74t;~'i7 )4~ C43 47pF I~II I I ":'" R63 4.7K YI HO ~:In 74LS92 ROIl) CTR ISHT I) L..........:<. o8 I 74LS93 8 AO AI C8 9 s rr CI6 14 ~ 117 ~ 74"LS74fZ42 10 I ~ I I I,.l.! I I I tl9 ~ '1'1 13 9 B f7.
