Unit installation

Chapter 1 Introduction Installation and Operation Manual
1-14 Functional Description FCD-E1
• In the input (transmit) direction, the user’s data applied to the input of the
channel interface is placed in the appropriate timeslots of the RSER line, under
the control of the management subsystem.
To enable synchronous operation, FIFO buffers are used to absorb small timing
variations (jitter, wander, etc.). In all the data channel timing modes, the FIFO size
is automatically selected in accordance with the data channel rate, as listed in
Table 1-2. The values listed in Table 1-2 are selected in accordance with the limits
specified in the applicable standards.
In addition, when using the DTE2 mode, the FIFO size can also be manually
selected, to enable the user to increase FIFO size when the jitter exceeds the
expected limits.
Table 1-2. FIFO Size versus Data Channel Rate
Data Channel Rate (kbps)
n × 56 n × 64
FIFO Size (bits)
56 64
±16
112 and 168 128 and 192
±30
224 through 448 256 through 512
±52
504 through 896 576 through 1024
±72
952 through 1792 1088 through 1792
±52
1848 and 1904 1856 and 1920
±30
1960 1984
±16
In addition to payload data, the data channel interfaces handle two additional
types of signals:
• Clock signals. The direction of the clock signals depends on the data channel
timing mode, DCE, DTE1, or DTE2. The timing modes are explained in the
Synchronous Data Port Timing section on page 1-6.
In the DTE2 mode, the clock signal applied to the transmit input is connected
to the clock bus and can be selected as an FCD-E1 system timing reference.
• Handshaking signals. The handshaking signals are used to control the exchange
of signals with the user’s equipment, in accordance with the protocol applying
to the installed data channel interface. The handshaking is performed under
the control of the management subsystem.
The functions of the handshaking signals are explained in the Data Channel
Interfaces section on page 1-4.
Ethernet Interface
For description of the IR-ETH and IR-ETH/Q interfaces, refer to Appendix E and
Appendix F, respectively.
The timing mode of the Ethernet channel interface is always DCE, that is, the timing
of the receive and transmit paths is always locked to the FCD-E1 system clock.