Specifications

Installation and Operation Manual Chapter 1 Introduction
ASMi-31 Ver. 3.0 Functional Description 1-7
• Memory (NOVRAM) – New configurations of the local and remote units are
saved by the CPU in the Non Volatile Random Access Memory (NOVRAM).
CPU requires other memory devices, such as EPROM, for proper functioning.
• PLL – The Phased Locked Loop (PLL) serves to synchronize the fast clock
generated by the internal oscillator with the external clock derived from the
DTE interface. This module is active only while the modem clock is set to EXT
mode.
• U-interface – The U-interface handles the following functions:
 Scramble the data received from serial bus, perform rate adaptation and
transfer the scrambled and rate-adapted data to the appropriate slot in
the superframe.
 Extract line data from the superframe, descramble the data and transfer
it to the serial bus.
 Recover the clock timing from the superframe, when in LBT mode.
 Recognize and perform commands included in the maintenance bit
received from the remote unit in the superframe, such as
activate/deactivate State Machine, transfer the D-channel, perform echo
canceling (EC) of the data transmitted to the line, using hybrid principles.
• Hybrid line transformer – The EC module in conjunction with the pulse
transformer form the passive line termination circuit. The circuit consists of
three blocks:

Hybrid network – this is a two to four wire converter providing a limited
cancellation of the near end echo.

Compensation circuit – increases the cut-off frequency in the receiver
path, in conjunction with the transformer.

Line pulse transformer – a llows passage of a sealing current and of
phantom feed supply through the secondary winding without causing flux
density saturation of the magnetic core, by being designed for low
inductance.
• BERT – Generates an internal pseudo random 511-bit test pattern per V.52
ITU standard to test the end-to-end connectivity.
• Power supply – Provides power to ASMi-31.