User manual

Table Of Contents
Publication No. 980935 Rev. M 3152B User Manual
Astronics Test Systems 3152B Specifications
A-3
Resolution 20 ns
Error 6 sample clock cycles + 150 ns
Re-trigger Delay
(Waveform end to waveform restart) 100 ns to 20 s
Resolution 20 ns
Error 3 sample clock cycles + 20 ns
Trigger Jitter ±1 sample clock period
Frequency/Time Accuracy
10 MHz Reference Source Internal, External, VXI backplane CLK10
Internal 0.0001% (1 ppm TCXO) initial tolerance from
19°C to 29°C; 1ppm/°C below 19°C and above
29°C; 1 ppm/year aging rate
External
Connector Front panel BNC:
3151B: REF IN
3152B: PM IN
3100M/R: EXT 10MHz
Impedance and Level 10 kΩ ±5%, TTL, 50% ±2% duty cycle, or 50 Ω
±5%, 0 dBm, manually selectable using internal
jumpers
External Sample Clock Source External, ECLTRG0
Connector Front panel BNC:
3151B & 3152B: CLOCK IN
3199M/R: EXT SCLK
Frequency External: DC to 250 MHz
ECLTRG0: DC to 66MHz
Impedance and Level 50 Ω ±5%, PECL or NECL
PLL Characteristics
Description Automatically locks 3152B output to external signal
applied to trigger port
PLL Input Characteristics Same as trigger input
External Lock Frequency Range Standard Waveforms: 500 Hz to 10 MHz
Arbitrary Waveforms: 500 Hz to 100 M/(points per
cycle)
Phase Control Coarse: ± 180º
Fine: ± 36º with 0.01 º resolution
Phase Control Accuracy ± 2% ±1 sample clock period
PM Characteristics
Description External signal offsets phase. Available in PLL
mode when unit is locked to an external signal.
PM Input Bandwidth 100 Hz-10 kHz
External Lock Frequency Range Standard Waveforms: 500 Hz to 10 MHz
Arbitrary Waveforms: 500 Hz to 100 M/(points per
cycle)
PM Input
Impedance 100 kΩ ±5%
Sensitivity 20º / V