Specifications

Specifications A-3
Internal Internal pro
g
rammable rate
g
enerator
S
y
stem Dela
y
From External Tri
gg
er input to Waveform Output
Standard Waveforms 120ns + 2 sample clock periods ± 1 sample clock period
Arbitrar
y
Waveforms 150ns + 2 sample clock periods ± 1 sample clock period
External Input from: 1) Front panel BNC, TTL compatible, positive slope
2) TTLTRG0-7, S
y
nchronous Protocol, ne
g
ative slope,
VXIbus TTLTRG tri
gg
er acceptor requirements:
Minimum pulse width (lo
g
ic low - asserted) : 20 ns,
Minimum pulse width (lo
g
ic hi
g
h - unasserted) : 20 ns,
External Output to: TTLTRG0-7, S
y
nchronous Protocol, ne
g
ative slope,
VXIbus TTLTRG tri
gg
er source requirements:
Minimum pulse width (lo
g
ic low - asserted) : 30 ns
Minimum pulse width (lo
g
ic hi
g
h - unasserted) : 80ns
Maximum Clock Frequenc
y
: 12.5 MHz
Note: For the external tri
gg
er output, the tri
gg
er source is the
pro
g
rammable S
y
nchronous Si
g
nal.
For tri
gg
er operation when s
y
nchronized, the tri
gg
er circuit in the master module has control of the sample
clock for all modules. Therefore, the master module must be tri
gg
ered before an
y
slave can output it's
waveform.
Back
p
lane Multi-Module S
y
nchronization
Multiple Model 3152 modules ma
y
be s
y
nchronized. A master Model 3152 module provides the necessar
y
si
g
nals to slave Model 3152 modules to achieve s
y
nchronization. The si
g
nals required are sample clock
(distributed on ECLTRG0) and another si
g
nal (distributed on ECLTRG1). Phase offset is settable (in de
g
rees)
for each slave module with respect to the master module output.
Phase Offset Resolution (P.O.R.) 360°/ Number of Points (min. # points = 10)
Phase Offset Ran
g
e 0° to 360° - 2880/n, where n = number of points
Phase Accurac
y
±[( 20 nS x 360°/PERIOD) + P.O.R.]
P.O.R. = phase offset resolution
PERIOD = 1/(output si
g
nal frequenc
y
)
Accurac
y
specified after PHAS:LOCK:NULL command
Jitter None
Front Panel Indicator LED’s
Fail Red - Power-up self-test failure
Access Amber - Module addressed on VXIbus
PLL On Amber - 3152 is locked to external si
g
nal
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