User`s manual

User’s Manual 43
Figure A-4 shows a typical timing diagram for the Rabbit 2000 microprocessor external
I/O read and write cycles.
Figure A-4. External I/O Read and Write Cycles—No Extra Wait States
T
adr
is the time required for the address output to reach 0.8 V. This time depends on the
bus loading. T
setup
is the data setup time relative to the clock. T
setup
is specified from
30%/70% of the V
DD
voltage level.
T
adr
T
adr
External I/O Read (no extra wait states)
CLK
A[15:0]
External I/O Write (no extra wait states)
CLK
A[15:0]
/IORD
valid
T1
Tw
T1
Tw
T2
valid
T2
/BUFEN
/IOCSx
/IOWR
/BUFEN
D[7:0]
valid
T
setup
T
hold
/CSx
/IOCSx
T
CSx
T
IOCSx
T
IORD
T
BUFEN
T
CSx
T
IOCSx
T
IORD
T
BUFEN
valid
D[7:0]
/CSx
T
CSx
T
IOCSx
T
IOWR
T
CSx
T
IOCSx
T
IOWR
T
BUFEN
T
BUFEN
T
DHZV
T
DVHZ