User`s manual

User’s Manual External Interrupts E–3
E.2 Single-Interrupt Request
Remove R26 and tie the inputs for external interrupt #1 and #0 together by adding a 1 kΩ resistor at R59.
Figure E–4 shows the locations of the resistors.
Under this configuration, shown in Figure E–5,
both interrupt #1 and #0 will be requested when an
edge is detected. The #1 interrupt will take place
first since it is of a higher priority.
The interrupt service routine for interrupt #1 should
ignore the interrupt. The actual service routine will
be the service routine for interrupt #0. If an interrupt
is lost, it will always be #1 and never #0. The 1 kΩ
resistor delays the edge slightly so that interrupt #1
is guaranteed to be latched earlier or simultaneously
with interrupt #0. It is important that the programmed
priority of interrupt #1 be higher than or equal to the
programmed priority of interrupt #0. Normally they
should be equal.
Spurious interrupts, which occur because of a fail-
ure to clear the request latch, are a possibility only if
there are other interrupts of higher priority than
external interrupt #1 and #0. These can only be the
result of programming one of the on-chip periph-
eral interrupts to have a higher interrupt priority.
This could be the case, for example, if the external
interrupts are programmed to have priority 1, and
one of the serial port interrupts is programmed to
have priority 2. Spurious interrupts can always be
eliminated by programming both external interrupts
to have a priority equal to the highest priority used
for another device. The priority can be reduced on
entry to the service routine to avoid blocking the
true high-priority interrupts. External interrupt #1
cannot cause interrupt #0 to have a spurious inter-
rupt or vice versa. In some cases, spurious interrupts
may not disturb function, but the fix is so simple
that it is not usually worth the trouble to analyze this
possibility.
Figure E–4: Locations of SMT Resistors to Change for External Interrupts
R19
R20
C17
C16
C15
C14
C13
R22
R21
R25
90
15
65
40
U4
R23
R24
R26
R29
C19
R38
R36
Y3
C20
R30
U5
U6
R31
R32
R33
R34
R35
R37
C22
Y2
R27 R28 C18
C21
R55
U10
R58
R59
C54
R57
R56
C53
JP1
J1
C52
C51
C50
R54 R53 R52 R51 R50
Top Side Bottom Side
R26
Flash
EPROM
R22
R58 R59
R25
R23
Figure E–5: RabbitCore RCM2100 Configuration
for Single-Interrupt Request
Interrupt Request #1
INT1A
Interrupt Request #0
INT0A
Edge
Detectors
1 kW
Interrupt Request
R59