User`s manual

B–2 Power Supply RabbitCore RCM2100 Series
Figure B–1 shows a schematic of the chip select cir-
cuit.
In a powered-up condition, the CS control circuit
must allow the processor’s chip select signal /CS1 to
control the SRAM’s CS signal /CSRAM. So, with
power applied, /CSRAM must be the same signal as
/CS1, and with power removed, /CSRAM must be
held high (but only needs to be as high as the battery
voltage). Q4 and Q5 are MOSFET transistors with
opposing polarity. They are both turned on when
power is applied to the circuit. They allow the CS
signal to pass from the processor to the SRAM so
that the processor can periodically access the
SRAM. When power is removed from the circuit,
the transistors will turn off and isolate /CSRAM
from the processor. The isolated /CSRAM line has a
100 kΩ pullup resistor to VRAM (R16). This pullup
resistor keeps /CSRAM at the VRAM voltage level
(which under no power condition is the backup bat-
tery’s regulated voltage at a little more than 2 V).
Transistors Q4 and Q5 are of opposite polarity so
that a rail-to-rail voltages can be passed. When the
/CS1 voltage is low, Q4 will conduct. When the
/CS1 voltage is high, Q5 will conduct. It takes time
for the transistors to turn on, creating a propagation
delay. This delay is typically very small, about 10 ns
to 15ns.
Figure B–1: Chip Select Circuit
/CS1
/CSRAM
/RESET
Q4
Q5
R14
R16
VRAM
VRAM
10 kW
100 kW