User`s manual

User’s Manual RabbitCore RCM2100 Specifications A–5
Figure A–3 shows a typical timing diagram for the Rabbit 2000 microprocessor memory read and write
cycles.
T
adr
is the time required for the address output to reach 0.8 V. This time depends on the bus loading. T
setup
is
the data setup time relative to the clock. Tsetup is specified from 30%/70% of the V
DD
voltage level.
Figure A–3: Memory Read and Write Cycles
T
adr
T
adr
Memory Read (no wait states)
/WE
T
hold
valid
CLK
A[19:0]
D[7:0]
valid
T
setup
T
hold
Memory Write (no extra wait states)
CLK
A[19:0]
D[7:0]
/CSx
valid
/OEx
/CSx
valid
/WEx
valid
T1
T2
T1
Tw
T2
valid