User`s manual

OP710048



 Hardware

RE (Receiver Enable)

This bit controls the receiver: 1 ⇒ enabled, 0 ⇒ disabled. When this bit is

cleared, the processor aborts the operation in progress, but does not disturb

RDRF or the error flags.

MPE (Multiprocessor Enable)

This bit (1 ⇒ enabled, 0 ⇒ disabled) controls multiprocessor communica-

tion mode which uses an extra bit for selective communication when a

number of processors share a common serial bus. This bit has effect only

when MP in Control Register B is set to 1. When this bit is 1, only bytes

with the MP bit on will be detected. Others are ignored. If this bit is 0, all

bytes received are processed. Ignored bytes do not affect the error flags or

RDRF.

ASCI Control Register B

Control Register B configures the multiprocessor mode, parity, and baud

rate for each channel.

SS (Source/Speed Select)

Coupled with the prescaler (PS) and the divide ratio (DR), the SS bits select

the source (internal or external clock) and the baud rate divider, as shown

in Table 3-4.

CNTLB0 (02H) and CNTLB1 (03H)

76543210

MPBT MP

/CTS

PEO DR SS2 SS1 SS0

R / W R / W R / W R / W R / W R / W R / W R / W

Table 3-4. Baud Rate Divide Ratios

for Source/Speed Select Bits

SS2 SS1 SS0 Divide Ratio

000 ÷ 1

001 ÷ 2

010 ÷ 4

011 ÷ 8

100 ÷ 16

101 ÷ 32

110 ÷ 64

1 1 1 external clock*

* May not exceed system clock ÷ 40