Specifications

DATA SHEET QF4A512
Rev D4, Dec 07 58 www.quickfiltertech.com
1400h FIR_0_1_DATA_RAM (FIR Data Memory, LSB)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Channel1 1400h C1D1_7 C1D1_6 C1D1_5 C1D1_4 C1D1_3 C1D1_2 C1D1_1 C1D1_0
Channel2 1800h C2D1_7 C2D1_6 C2D1_5 C2D1_4 C2D1_3 C2D1_2 C2D1_1 C2D1_0
Channel3 1C00h C3D1_7 C3D1_6 C3D1_5 C3D1_4 C3D1_3 C3D1_2 C3D1_1 C3D1_0
Channel4 2000h C4D1_7 C4D1_6 C4D1_5 C4D1_4 C4D1_3 C4D1_2 C4D1_1 C4D1_0
(C1D1_0 - C1D1_7): Represents the LSB of a 16 bit value of in this case TAP1, Channel 1 of the computed FIR filter data.
Description: These are the memory locations of the temporary stored data of each tap as the signal is multiplied and
accumulated.
The next unique Tap value would start at 1402h, Tap3 would start at 1404h and so on for all of the computed Taps.
Channel 2: FIR_1_1_DATA_RAM Address 1800h
Channel 3: FIR_2_1_DATA_RAM Address 1C00h
Channel 4: FIR_3_1_DATA_RAM Address 2000h
1401h FIR_0_1_DATA_RAM (FIR Data Memory, MSB)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Channel1 1401h C1D1_15 C1D1_14 C1D1_13 C1D1_12 C1D1_11 C1D1_10 C1D1_9 C1D1_8
Channel2 1801h C2D1_15 C2D1_14 C2D1_13 C2D1_12 C2D1_11 C2D1_10 C2D1_9 C2D1_8
Channel 1C01h C3D1_15 C3D1_14 C3D1_13 C3D1_12 C3D1_11 C3D1_10 C3D1_9 C3D1_8
Channel4 2001h C4D1_15 C4D1_14 C4D1_13 C4D1_12 C4D1_11 C4D1_10 C4D1_9 C4D1_8
(C1D1_8 - C1D1_15): Represents the MSB of a 16 bit value of in this case TAP1, Channel 1 of the computed FIR filter data.
Description: These are the memory locations of the temporary stored data of each tap as the signal is multiplied and
accumulated. For internal use only.
The next unique Tap value would start at 1403h, Tap3 would start at 1405h and so on for all the computed Taps.
Channel 2: FIR_1_0_DATA_RAM Address 1801h
Channel 3: FIR_2_0_DATA_RAM Address 1C01h
Channel 4: FIR_3_0_DATA_RAM Address 2001h