Specifications

DATA SHEET QF4A512
Rev D4, Dec 07 44 www.quickfiltertech.com
Address 26h X X X pmux_srst arec_srst spim_rst iIgc_srst pcg_srst
*0 = Default
1 = Reset
Description: Soft reset of internal blocks. User resets can be performed in register FULL_SRST (02h).
27h ADC_CTRL (ADC control) - LOCKED
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Address 27h X X X X afe_dcr_en afe_adc_shin afe_sub_samp1 afe_sub_samp0
28h AREC_CTRL (ADC Pipeline latency) - LOCKED
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Address 28h X X X X D3 D2 D1 D0
Description: Programmable ADC pipeline latency. Default value is 9, allowable range is 6 – 10.
29h PMUX (Test Mux) – Factory use only (Default value = 0)
2Ah DEBUG (Debug mode) – Factory use only (Default value = 0)
2Bh PCG_MNTNC (PCG maintenance) – Factory use only (Default value = 0)
2Ch CAL_AFE (AFE Calibration) – Factory use only (Default value = 1)
2Dh BIST_CTRL (BIST control) – Factory use only (Default value = 0)
2Eh BIST_STATUS_0 (BIST status) – Factory use only (Default value = 0)
2Fh BIST_STATUS_1 (BIST status) – Factory use only (Default value = 0)
12.7 Channel-specific Registers
Table 19. Channel-specific Register Map
Channel
1
Channel
2
Channel
3
Channel
4
Function
0030h -
0031h
0060h -
0061h
0090h -
0091h
00C0h –
00C1h
Run & Status
0032h –
0050h
0062h –
0080h
0092h –
00B0h
00C2h –
00E0h
Configuration
0051h –
0059h
0081h –
0089h
00B1h –
00B9h
00E1h –
00E9h
Maintenance
005Ah –
005Fh
008Ah –
008Fh
00Bah –
00BFh
00EAh –
00EFh
Reserved
The following descriptions show the address for Channel 1. The maps for the other three channels are identical with address offsets of
30h for Channel 2, 60h for Channel 3 and 90h for Channel 4, as shown in the table above.