Specifications

DATA SHEET QF4A512
Rev D4, Dec 07 40 www.quickfiltertech.com
adc_unN
* 0 = No underflow.
1 = ADC underflow, out of range, low.
Description: Indicates an underflow condition for the ADC on channel N.
12.5 Global Configuration Registers
Table 17. Control Register listing (Global Configuration)
Hex* Register Name Description
0011h PLL_CTRL_0 PLL Pre-divider, frequency range.
0012h PLL_CTRL_1 PLL loop divider.
0013h ADC_CLK_RATE Clock rate for ADC, CRC and AREC.
0014h SYS_CLK_CTRL System Clock control.
0015h SPI_CTRL Set single-, multi-channel mode
0016h SPI_MON Monitor internal data transfers
0017h EE_STADDR EE start address for block transfers (byte0)
0018h EE_STADDR EE start address for block transfers (byte1)
0019h CHIP_STADDR Chip start address for block transfers (byte0)
001Ah CHIP_STADDR Chip start address for block transfers (byte1)
001Bh END_ADDR Ending address for block transfers (byte0)
001Ch END_ADDR Ending address for block transfers (byte1)
11h PLL_CTRL_0 (PLL pre-divider and range)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Address 11h X pll_range pll_m5 pll_m4 pll_m3 pll_m2 pll_m1 pll_m0
pll_m
Description: A 6-bit number designating the value of the PLL pre-divider (M). Default value is 1.
pll_range
0 = 20 – 100 MHz
*1 = 100 – 200 MHz
Description: Set the range of the PLL clock which supplies the ADC and system clocks.
12h PLL_CTRL_1 (PLL loop divider)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Address 12h X X pll_n5 pll_n4 pll_n3 pll_n2 pll_n1 pll_n0
Pll_n
Description: A 6-bit number designating the value of the PLL loop divider (N). Default value is 10.
13h ADC_CLK_RATE (ADC Clock Rate)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Address 13h X X X X X afe_clk_inv adcclk_rate1 adcclk_rate0