Specifications

DATA SHEET QF4A512
Rev D4, Dec 07 37 www.quickfiltertech.com
* 0 = Configure mode.
1 = Run mode
Description: In Run mode automatically starts filtering and sending out filtered data on the SIF interface.
Note: Bits 2 and 3 must be left at their default value of 0.
eeclk_rate
000 (110, 111) = XTAL frequency
001 = XTAL frequency/2
010 = XTAL frequency/4
011 = XTAL frequency/8
*100 = XTAL frequency/16
101 = XTAL frequency/32
Description: Clock Rate for EEPROM data transfer. Frequency is divided down as shown above. Maximum value is 5, higher values if
written will default back to 000.
alt_startup2
Description: Selects alternate values for STARTUP_2 register. Default value is 0.
08h STARTUP_ 2 (Initialization delay counter)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Address 08h init_dly7 init_dly6 init_dly5 init_dly4 init_dly3 init_dly2/ xtnd_init init_dly1 / P1 init_dly0 / P0
init_dly
* 10h = Delay count
Description: Delay counter for the initialization and general control
xtnd_init
Description: If alt_startup2 AND xtnd_init bits are set, calls for extended initialization (e.g. load calibration settings)
P0, P1
Description: Reserved for future use.
12.4 Run and Status Registers
09h ENABLE_0 (ADC Enable)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Address 09h pcg_ch4_en pcg_ch3_en pcg_ch2_en pcg_ch1_en X X pll_pdn osc_enable
osc_enable
0 = Powered Down
*1 = Oscillator enabled
Description: Enables the crystal oscillator (or external clock if configured).
PLL_enable
0 = Powered Down
*1 = PLL enabled
Description: Enables the phase locked loop.