Specifications

DATA SHEET QF4A512
Rev D4, Dec 07 35 www.quickfiltertech.com
02h FULL_SRST (Global Soft Reset)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Address 02h X X X X X X X glbl_srst
glbl_srst
* 0 = Does nothing.
1 = Reset
Description: Activates all soft resets. The reset value of this register is zero, regardless of the data in the corresponding EEPROM
address.
03h GLBL_CH_CTRL (Global Channel Control)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Address 03h ch4_pwrd ch3_pwrd ch2_pwrd ch1_pwrd ch4_srst ch3_srst ch2_srst ch1_srst
chN_srst
* 0 = Does nothing.
1 = Reset
Description: Activates all soft resets on a per channel basis.
chN_pwrd
* 0 = Does nothing.
1 = Disable/power down
Description: Turns on or off each channel.
Note: The reset value of this register is zero, regardless of the data in the corresponding EEPROM address.
04h RUN_MODE (Serial Interface Run mode)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Address 04h X X X X X X X run_mode
run_mode
* 0 = Configure mode.
1 = Run mode.
Description: Sets the serial interface (SPI) to either configure or run mode. The reset value of this register is zero, regardless of the data
in the corresponding EEPROM address. However, if auto_run and auto_config bits are set the chip will write this register to 1 after a
reset (see STARTUP_1 Register, 07h).
12.3 EEPROM Startup Registers
05h EE_TRANS (EEPROM Transfer) – AUTO CLEAR
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Address 05h X X X X X rd_status wr_strt rd_strt
rd_strt