Specifications

DATA SHEET QF4A512
Rev D4, Dec 07 30 www.quickfiltertech.com
In Configure mode 14-bit address words are used. In Run mode 8-bit addressing is used. These differences are shown graphically in
the following diagram. Consequently the host controller must use the appropriate timing depending on which mode of operation is
active. (At power up the mode of operation is determined by the value of the auto_start bit (register STARTUP_1).
Figure 13. Comparison of Configure and Run Mode Timing
If it is unknown which mode is active there are several ways to determine this. If in Run mode there should be a continuous stream of
conversions occurring which should be reflected by changes in level of the DRDY pin, furthermore if SCLK is active and CSN is held
low there should be transitions occurring on the SDO pin. These pins can me monitored for activity within a pre-determined timeout
interval. These methods are summarized below.
1. If the QF4A512 is in Run mode, DRDY will be driven high when the fastest sample is available. If in Configure mode, DRDY is
an input (internal pull-down in the chip). So, by monitoring DRDY you can determine the mode of operation.
2. Holding SDI low (to prevent inadvertently writing any bad info to the chip), toggle SCLK and look for data on SDO. If in
Configure mode, SDO will be low the whole time. If in Run mode, SDO will eventually toggle.
10.5 Multiple QF4A512s and Synchronous Sampling
A single QF4A512 can sample 4 analog signals simultaneously. However, some applications sample more than 4 channels using
multiple QF4A512 chips. Multi-chip configurations of QF4A512 are described in App Note QFAN005 “Multiple Chip Configuration”.
Some systems additionally require that the samples across multiple chips be tightly synchronized. App Note QFAN020 “Synchronized
Sampling Using Multiple QF4A512 Programmable Signal Converters” describes a simple additional procedure to synchronize multiple
QF4A512 devices so that all analog signals are sampled at the same moment and all DRDY signals assert synchronously.
SCLK (i/p)
Configure Mode Writes
CSN (i/p)
DRDY (i/p)
0
SDI (i/p)
SDO (o/p)
14-bit address
8-bit write data
23222120191817161514131211109876543210Bit #
Run Mode Writes :
Single Channel
1514131211109876543210
8-bit address 8-bit write data
16-bit ch N filter data
SCLK (i/p)
CSN (i/p)
DRDY (o/p)
SDI (i/p)
SDO (o/p)
Bit #
15 14 13 12 11 10 9 8
8-bit address
16-bit ch N filter data
SCLK (i/p)
Run Mode Writes :
Multiple Channels
CSN (i/p)
DRDY (o/p)
SDI (i/p)
SDO (o/p)
16-bit ch N filter data
23
Bit #
222120191817161514131211109876543210
8-bit address 8-bit write data
p i1 i0
n
0000
8-bit write data