Specifications

DATA SHEET QF4A512
Rev D4, Dec 07 26 www.quickfiltertech.com
Note, this data applies to SO and SI depending whether it is being read or written.
Figure 9. Configure Mode Timing, Read and Write
Figure 10. Configure Mode Timing – Multiple Read / Write
Note that Configure mode registers wider than 8 bits must be written completely starting at the low address.
SCLK (i/p)
Configure Mode : Single Read Access
CSN (i/p)
DRDY (i/p)
1
SDI (i/p)
Notes:
> SDI is captured on the rising edge of SCLK
> SDO transitions after the falling edge of SCLK
> SDO is tri-stated when CSN is high
denotes a “don’t care”
SDO (o/p)
14-bit address
8-bit read data
SCLK (i/p)
Configure Mode : Single Write Access
CSN (i/p)
DRDY (i/p)
0
SDI (i/p)
SDO (o/p)
14-bit address 8-bit write data
23
Bit #
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Bit #