Specifications

DATA SHEET QF4A512

Rev D4, Dec 07 25 www.quickfiltertech.com

The QF4A512 is designed to interface directly with the serial peripheral interface (SPI) of microcontrollers and Digital Signal

Processors. The QF4A512 always operates in SPI slave mode where SDI is the input serial data, and SDO is the output serial data.

SCLK is the input serial clock maximum 40 MHz.

In order to address and write to the QF4A512, /CS is asserted low. When the device is not selected, data will not be accepted via the

serial input pin (SDI) and the serial output pin (SDO) will remain in a high impedance state.

There are two primary modes of bus operation for the QF4A512, “configure” mode, and “run” mode. The required mode is selected by

writing the run_mode bit in the RUN_MODE register (04h).

“Configure” mode is used to set up or change options in the QF4A512. In this mode it is possible to read/write the control registers and

the coefficient RAMs. It is also possible to initiate transfers of data between the registers/RAM and the EEPROM. DRDY will be held

low by an internal pulldown in this mode.

“Run” Mode is used to send the filtered data out of the QF4A512 via the SDO pin. In “Run” mode the Data Ready, DRDY, pin is used

as a data rate output derived from the highest channel sampling rate.

A third, “EEPROM” mode is available for transfers directly from the SPI bus to/from the EEPROM. This mode is intended for bulk

programming of devices. “EEPROM” mode is entered by first setting the device into “Configure” mode, then by pulling high the

DRDY/SEL pin. Further information on the use of this mode is documented in Application Note QFAN007, “Bulk Programming

EEPROM”.

10.2 Configure Mode

By setting the run_mode bit to 0 the QF4A512 is in Configure mode, ready for setup and programming. General parameters include

things such as auto start, auto configure, and unique channel setup. In this mode the bus has access to the full 14-bit on-chip address

space which includes all the internal registers, coefficient and data RAMs.

Once the QF4A512 has been programmed, the register and coefficient RAM data can be transferred to EEPROM for non-volatile

storage. A single command is provided to transfer the data from all of the internal registers and filter coefficients. A complementary

command is also available to copy back all the data from EEPROM to the registers and RAM. This command may be invoked

automatically at device power on and rest by configuring the Startup register.

Partial, block, transfers can be performed by specifying the desired starting and ending memory locations. This method is particularly

useful for accessing the user data from EEPROM – 128bytes in total are available in EEPROM but they must be accessed in 8 byte

blocks from the SPI bus.

Figure 8. Configure Mode Format

Table 7. Configure Mode, Register Address Decoding SDI (0000h-3FFF)

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

R/W

Addr

R/W = Write is 0, Read is 1

X = Don't Care

(Addr13 - Addr0) = Command Address

Table 8. Configure Mode, Register Data (00h-FFh)

D7 D6 D5 D4 D3 D2 D1 D0

Data7 Data6 Data5 Data4 Data3 Data2 Data1 Data0

(Data7 - Data0) = Unique data per command.

read/write_n

Configure Mode Format : Single Access

write data(8)

address(14)

read data(8)