Specifications

DATA SHEET QF4A512
Rev D4, Dec 07 23 www.quickfiltertech.com
8.3 FIR Latency
There will be a delay introduced to the signal as it passes through the QF4A512. There are several components to this latency:
1. PGA and AAF = If sample frequency F
S
is greater than 800kHz add 0.122uS, else add 0.667uS
2. ADC = 12/ADC Clock rate
3. CIC = (Number of Channels*4/ADC Clock rate)+(5/(4*F
S
))
4. G = (G number of taps – 1) / (2*G_F
S
) = 7 / (4*F
S
)
5. H = (H number of taps – 1) / (2*H_F
S
) = 44/(2*F
S
)
6. FIR filters = (Number of taps – 1) / (2*F
S
)
The dominant influence on the overall latency will be number of taps in FIR filter.
Download Quickfilters QF4A512 Latency Calculator from our website at www.quickfiltertech.com this excel spreadsheet based
calculator will give you immediate accurate results. QFPro Software also shows the latency during configuration.
8.4 Maximum number of taps
There may be situations where it is not possible to implement a filter using all 512 taps. Quickfiters QFPro software limits the number of
taps you can use if the design approaches the maximum limits. At high sampling rates it may not be possible to implement all 512 taps
within the maximum available sys_clk rate. The FIR processes two taps per sys_clk and requires 4 additional clocks to fill the processor
pipeline. The equation which determines the max taps is as follows:
Max Taps = 2 * Sys_clk/f
s
- 4
Example: sys_clk = 200MHz (max allowed value), fs = 2MHz → Maximum number of taps = 196.
Figure 6. Maximum Taps vs. Sample Rate vs. Sys Clk
9. SYSTEM CLOCKS
The master clock for the QF4A512 is produced by a crystal oscillator with a nominal frequency of 20MHz. Alternatively, the device can
be fed with an external clock signal derived elsewhere. The master clock is used as a reference for a phase-locked loop (PLL), from
10
100
1000
10000
100000
1000000
10000000
0 100 200 300 400 500 600
Maximum # Of Taps
Input Sample Rate (Hz)
200 MHz Sys Clk Rate
100 MHz
50 MHz
25 MHz
12.5 MHz
6.25 MHz
3.125 MHz