Specifications

DATA SHEET QF4A512
Rev D4, Dec 07 19 www.quickfiltertech.com
7. ANALOG TO DIGITAL CONVERTER
7.1 Overview
The ADC has a pipeline architecture that is 12 bits in hardware and runs at up to 100Msps. Resolutions of up to 16 bits are achieved by
oversampling the input and averaging the resultant conversions. With INL and DNL of +/- 1LSB, 16 bit linearity is achieved. During Chip
Configuration and Filter Design, the exact sampling speed of the ADC is determined (based on the highest sampling rate required for
any one of the four channels).
Not shown in the block diagram are the following sub-blocks which handle decimation/down-conversion of the oversampled data:
CIC (Cascaded Integrator Comb Filters)
The purpose of the CIC stage is the integration of 16 bits, and adjustment of the proper sample rate through decimation. The
digitized signal is then processed in the CIH (Cascaded Integrator Halfband Filters)
CIH (Cascaded Integrator Halfband Filters)
The purpose of the CIH stage (not shown in block diagram) is droop recovery to compensate for the frequency response of the
CIC filter. After moving through the CIH, the signals are sent into the FIR (Finite Impulse Response Filter) for user filtering.
7.2 Sampling Rates / ENOB
The QF4A512 features a very flexible architecture allowing tradeoffs between resolution, sampling rate and accuracy. The combination
of the ADC sampling rate, subsequent down-conversion in the CIC/CIH blocks and number of active input channels will determine the
effective sampling rate, (
f
S
), or each input channel. The effective sampling rate is the parameter which limits the overall input
bandwidth, according to Nyquist. The table illustrates several different configurations and performance levels for various ADC clock
rates.
Table 1. Example sampling rates and ADC clock frequency
ADC clock
(
f
ADC,
MHz)
Oversampling
Rate
Effective
Sampling Rate
(
f
S
)
Aggregate.
BW *
Data
Output
(bits)
12.5 6248 2 kHz 909 Hz 16
12.5 624 20 kHz 9.09 kHz 16
25 128 201.6 kHz 91.6 kHz 16
50 24 2.08 MHz 945 kHz 16
100 48 2.08 MHz 945 kHz 16
* The aggregate bandwidth is equal to the effective sampling rate divided by 2.2.
Although the ADC is 12-bits in hardware, the effective resolution can be increased by oversampling. Theoretically, a 4x increase in the
oversampling rate increases the effective resolution by 1 bit. Decimation within the converter always results in 16-bit output data words,
regardless of oversampling rate. Beyond a certain limit, determined by the noise and distortion performance of the device, the effective
number of bits (ENOB) does not increase any further. For the QF4A512, oversampling rates above 100 have been coded into the
Quickfilter Pro Software (“Optimize Precision”) to provide optimum performance.
Depending on the application and frequencies of interest it may be more meaningful to refer to the SNR, SFDR or THD in Electrical
Characteristics, for a more accurate reflection of overall system performance.
The ADC clock rate (Register ADC_CLK_RATE) is always the same for all four channels. However, the oversampling rate can be
varied on a per-channel basis. Oversampling by a factor of 4 always occurs in the CIH block, additional oversampling occurs according
to the value of “R” in the CIC block. The effective sampling rate (
f
S
) for each channel is given by the following formula:
f
S
= f
ADC
/ (4 x R x N)
R = CIC “R” value (register CIC_n_R , n = channel number)
N = Number of active channels
There are many more combinations of ADC clock rate and CIC R values than shown in the table. The Quickfilter Pro software will
chose optimum values for each depending on the filter characteristics specified for each of the configured channels. The resulting
parameters can be reviewed in the software, and also reviewed by examining the QF4A512’s register contents.
7.3 Aggregate Bandwidth