Specifications

DATA SHEET QF4A512
Rev D4, Dec 07 11 www.quickfiltertech.com
3. GENERAL DESCRIPTION
Figure 1. Functional Block Diagram
3.1 Analog Front End (AFE)
The AFE consists of a Programmable Gain Amplifier (PGA), a chopper-stabilized amplifier and an Anti-Aliasing Filter.
Programmable Gain Amplifier (PGA)
The PGA can be set at gains of 1X, 2X, 4X, and 8X. The input impedance of the PGA is 10kΩ on both the positive and negative
inputs. The PGA can be configured as either single ended or differential and can receive inputs of up to 2.0V p-p directly. With a
single scaling resistor in each channel, two if configured differentially, the PGA can receive signals of up to +/- 10Vp-p or higher.
Chopper-stabilized Amplifier (not shown in diagram)
This circuit minimizes correlated (1/f) noise and dc offset within the chip. For sampling rates less than 200kHz this circuit will
maximize signal-to-noise performance, and hence SINAD and ENOB. (see Section 6.2)
Anti-Aliasing Filter (AAF)
The Anti-Aliasing Filter is designed to reject frequencies that are higher than the band of interest. If those frequencies are sent to
the ADC, they can alias back into the band of interest and can cause erroneous readings to result. The AAF is a 3rd order Bessel
function (linear phase) and is set to the appropriate cut-off frequency based on the filter design that is implemented. The AAF has
two available cut off frequencies, 500kHz and 3MHz.
3.2 Analog to Digital Converter (ADC)
The ADC has a pipeline architecture that is 12 bits in hardware and runs at up to 100Msps. Resolutions of up to 16 bits are achieved by
oversampling the input and averaging the resultant conversions. During Chip Configuration and Filter Design, the exact sampling speed
of the ADC is determined (based on the highest sampling rate required for any one of the four channels).
Not shown in the block diagram are the following sub-blocks which handle decimation/down-conversion of the oversampled data:
CIC (Cascaded Integrator Comb Filters)
The purpose of the CIC filter is the integration of 16 bits, and adjustment of the proper sample rate through decimation. The
digitized signal is then processed in the CIH (Cascaded Integrator Halfband Filters)
CIH (Cascaded Integrator Halfband Filters)