Service Guide

LTE-A Module Series
EM060K-GL&EM120K-GL_Hardware_Design 40 / 78
AC coupling capacitors C5 and C6 must be placed close to the host and close to each other. C1 and C2
have been integrated inside the module, so do not place these two capacitors on your schematic and
PCB. To ensure the signal integrity of USB 2.0 data traces, R1, R2, R3 and R4 must be placed close to
the module, and the stubs must be minimized in PCB layout.
Please follow the principles below when designing for the USB interface to meet USB 3.0 and 2.0
specifications:
 Route the USB signal traces as differential pairs with ground surrounded. The impedance of
differential trace of USB 2.0 and USB 3.0 is 90 Ω.
 For USB 2.0 signal traces, the trace length should be less than 120 mm, and the differential data pair
matching should be less than 2 mm. For USB 3.0 signal traces, length matching of each differential
data pair (Tx/Rx) should be less than 0.7 mm, while the matching between Tx and Rx should be less
than 10 mm.
 Do not route signal traces under crystals, oscillators, magnetic devices, other high-speed and RF
signal traces. Route the USB differential traces in inner-layer of the PCB, and surround the traces
with ground on that layer and with ground planes above and below.
 Junction capacitance of the ESD protection device might cause influences on USB data lines, so you
should pay attention to the selection of the device. Typically, the stray capacitance should be less
than 1.0 pF for USB 2.0, and less than 0.15 pF for USB 3.0.
 Keep the ESD protection devices as close to the USB connector as possible.
 If possible, reserve 0 Ω resistors on USB_DP and USB_DM traces respectively.
4.3. PCM Interface*
The module supports audio communication with external codec via Pulse Code Modulation (PCM) digital
interface. The PCM interface supports the following modes:
 Primary mode (short frame synchronization): the module works as both master and slave
 Auxiliary mode (long frame synchronization): the module works as master only
In primary mode, the data is sampled on the falling edge of the PCM_CLK and transmitted on the rising
edge. The PCM_SYNC falling edge represents the MSB. In this mode, the PCM interface supports
256 kHz, 512 kHz, 1024 kHz or 2048 kHz PCM_CLK at 8 kHz PCM_SYNC, and also supports 4096 kHz
PCM_CLK at 16 kHz PCM_SYNC.
In auxiliary mode, the data is sampled on the falling edge of the PCM_CLK and transmitted on the rising
edge. The PCM_SYNC rising edge represents the MSB. In this mode, PCM interface operates with a
256 kHz PCM_CLK and an 8 kHz, 50 % duty cycle PCM_SYNC only.
The module supports 16-bit linear data format. The following figures show the primary mode’s timing
relationship with 8 kHz PCM_SYNC and 2048 kHz PCM_CLK, as well as the auxiliary mode’s timing