Product Info

5G Module Series
RM502Q-GL Hardware Design
RM502Q-GL_Hardware_Design 37 / 77
VCC
FULL_CARD_POWER_OFF#
Module power-on or insertion detection
RESET_N
RFFE_VIO_1V8
System turn-on and booting
V
IH
≥ 1.19 V
23 ms
PCIE_CLKREQ_N
PCIE_RST_N
PCIE_REFCLK
T
PVPGL
> 50 ms
t
turn-on
68 ms
33 ms
t
power-on
T
PERST#-CLK
> 100 us
Figure 23: PCIe Power-on Timing Requirements of the Module
The following principles of PCIe interface design should be complied with, so as to meet PCIe V2.1
specification.
⚫ Do not route signal traces under crystals, oscillators, magnetic devices or RF signal traces.
⚫ It is important to route the PCIe differential signal traces in inner layer of the PCB, and surround the
traces with ground on that layer and with ground planes above and below.
⚫ For PCIe signal traces, the recommended maximum length for TX and RX differential data pairs is
less than 250 mm, and the intra-lane length matching of TX and RX differential data pairs is less than
0.7 mm (5 ps).
3.8.2. USB Version and PCIe Version
Begin with ES2 (Engineering Samples 2), RM502Q-GL supports USB version and PCIe only version
described as below:
USB version
⚫ Support all USB 2.0/3.1 features
⚫ Support MBIM/QMI/QRTR/AT
⚫ Support switch between USB and PCIe by AT command
USB is the default communication interface between RM502Q-GL module and a host. If PCIe interface is
desired, an AT command under USB interface mode could be used. For more details about the AT
command, please refer to document [2].
It is suggested that USB 2.0 interface could be reserved for firmware upgrade.