Product Info

5G Module Series
RM502Q-GL Hardware Design
RM502Q-GL_Hardware_Design 13 / 77
2.3. Functional Diagram
The following figure shows a block diagram of RM502Q-GL.
Baseband
PMIC
Sub
-6 GHz
Transceiver
ANT0
ANT3
ANT2_GNSSL1
ET
VCC
RESET_N
38.4M
XO
SPMI
IQ
Control
Tx
PRx
DRx
PCI Express
M.2 Key
-B Interface
FULL_CARD_POWER_OFF#
W_DISABLE2#
USB 2.0 & USB 3.1
(U)SIM1
WWAN_LED#
WAKE_ON_WAN#
NAND Flash 4Gb x 8
LPDDR4 SDRAM 4Gb x 16
RFFE
W_DISABLE1#
GPIOs
Tx/Rx Blocks
ANT1
PCIe × 1
(U)SIM2
GND
Figure 1: Functional Diagram
RoHS
All hardware components are fully compliant with EU RoHS directive
NOTES