RM502Q-GL Hardware Design 5G Module Series Rev. RM502Q-GL_Hardware_Design_V1.0 Date: 2020-07-06 Status: Preliminary www.quectel.
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5G Module Series RM502Q-GL Hardware Design About the Document Revision History Version Date Author Description 1.
5G Module Series RM502Q-GL Hardware Design Contents About the Document ................................................................................................................................... 2 Contents ....................................................................................................................................................... 3 Table Index ...................................................................................................................................
G Module Series RM502Q-GL Hardware Design 3.12. Antenna Tuner Control Interface* ............................................................................................. 45 3.13. Configuration Pins ..................................................................................................................... 46 4 GNSS Receiver ................................................................................................................................... 47 4.1. General Description .........
5G Module Series RM502Q-GL Hardware Design Table Index Table 1: Frequency Bands and GNSS Type of RM502Q-GL Module ....................................................... 10 Table 2: Key Features of RM502Q-GL ...................................................................................................... 11 Table 3: Definition of I/O Parameters......................................................................................................... 17 Table 4: Pin Description ..........................
5G Module Series RM502Q-GL Hardware Design Figure Index Figure 1: Functional Diagram ..................................................................................................................... 13 Figure 2: Pin Assignment ........................................................................................................................... 16 Figure 3: Power Supply Limits during Radio Transmission .......................................................................
5G Module Series RM502Q-GL Hardware Design Figure 42: Top and Bottom Views of the Module....................................................................................... 74 Figure 43: Tray Size (Unit: mm) ................................................................................................................. 75 Figure 44: Tray Packaging Procedure .......................................................................................................
5G Module Series RM502Q-GL Hardware Design 1 Introduction This document defines RM502Q-GL module and describes its air interface and hardware interfaces which are connected with customers’ applications. This document helps customers quickly understand the interface specifications, electrical and mechanical details, as well as other related information of RM502Q-GL module. To facilitate its application in different fields, reference design is also provided for reference.
5G Module Series RM502Q-GL Hardware Design 1.1. Safety Information The following safety precautions must be observed during all phases of operation, such as usage, service or repair of any cellular terminal or mobile incorporating RM502Q-GL module. Manufacturers of the cellular terminal should notify users and operating personnel of the following safety information by incorporating these guidelines into all manuals of the product.
5G Module Series RM502Q-GL Hardware Design 2 Product Concept 2.1. General Description RM502Q-GL is a 5G NR/LTE-A/UMTS/HSPA+ wireless communication module with receive diversity. It provides data connectivity on 5G NR SA and NSA, LTE-FDD, LTE-TDD, DC-HSDPA, HSPA+, HSDPA, HSUPA and WCDMA networks with standard PCI Express M.2 interface. It supports embedded operating systems such as Windows, Linux and Android, and also provides GNSS and voice functionality to meet specific application demands.
5G Module Series RM502Q-GL Hardware Design RM502Q-GL can be applied in the following fields: ⚫ ⚫ ⚫ ⚫ ⚫ ⚫ ⚫ Rugged tablet PC and laptop computer Remote monitor system Vehicle system Wireless POS system Smart metering system Wireless router and switch Other wireless terminal devices 2.2. Key Features The following table describes key features of RM502Q-GL. Table 2: Key Features of RM502Q-GL Feature Details Function Interface PCI Express M.2 Interface Power Supply Supply voltage: 3.135–4.
5G Module Series RM502Q-GL Hardware Design B1/B2/B3/B4/B7/B25/B30/B38/B39/B40/B41/B42/B43/B48/B66 LTE: Max 1.0 Gbps(DL)/200 Mbps (UL) UMTS Features Support 3GPP R8 DC-HSDPA, HSPA +, HSDPA, HSUPA and WCDMA Support QPSK, 16QAM and 64QAM modulation DC-HSDPA: Max 42 Mbps (DL) HSUPA: Max 5.
5G Module Series RM502Q-GL Hardware Design RoHS All hardware components are fully compliant with EU RoHS directive NOTES 1. 2. 3. 4. 1) HPUE is only for single carrier. Within operation temperature range, the module meets 3GPP specifications. 3) Within extended temperature range, the module remains the ability to establish and maintain functions such as voice, SMS, data transmission without any unrecoverable malfunction.
5G Module Series RM502Q-GL Hardware Design 2.4. Evaluation Board To help with the development of applications conveniently with RM502Q-GL, Quectel supplies the evaluation board (PCIe Card EVB), a USB to RS-232 converter cable, a USB type-C cable, antennas and other peripherals to control or test the module. For more details, please refer to document [1].
5G Module Series RM502Q-GL Hardware Design 3 Application Interfaces The physical connections and signal levels of RM502Q-GL comply with PCI Express M.2 specification. This chapter mainly describes the definition and application of the following interfaces/pins of RM502Q-GL: ⚫ ⚫ ⚫ ⚫ ⚫ ⚫ ⚫ ⚫ ⚫ Power supply (U)SIM interfaces USB interface PCIe interface PCM interface* Control and indication interfaces* COEX UART interface* Antenna tuner control interface* Configuration pins NOTE “*” means under development.
5G Module Series RM502Q-GL Hardware Design 3.1. Pin Assignment The following figure shows the pin assignment of RM502Q-GL. The top side contains RM502Q-GL module and antenna connectors. No.
5G Module Series RM502Q-GL Hardware Design 3.2. Pin Description Table 3: Definition of I/O Parameters Type Description AI Analog Input AO Analog Output DI Digital Input DO Digital Output IO Bidirectional OD Open Drain PI Power Input PO Power Output The following table shows the pin definition and description of RM502Q-GL. Table 4: Pin Description Pin No. M.2 Socket 2 PCIe-based Pinout RM502Q-GL Pin Name I/O Description 1 CONFIG_3 CONFIG_3 DO Not connected internally 2 3.
5G Module Series RM502Q-GL Hardware Design (I)(0/1.8 V) module is turned off. When it is at high level, the module is turned on. 100k Ω resistor 7 USB_D+ USB_DP AI, AO USB 2.0 differential data (+) 8 W_DISABLE1# (I)(0/1.8 V) W_DISABLE1# DI Airplane mode control. Active LOW. 9 USB_D- USB_DM AI, AO USB 2.0 differential data (-) 10 GPIO_9/LED_1# (OD)(0/3.
5G Module Series RM502Q-GL Hardware Design 28 GPIO_8 /AUDIO_3 PCM_SYNC IO PCM data frame sync 29 PETn1 USB_SS_TX_M AO USB 3.1 transmit data (-) 30 UIM_RESET(O) USIM1_RST DO (U)SIM1 card reset 31 PETp1 USB_SS_TX_P AO USB 3.1 transmit data (+) 32 UIM_CLK(O) USIM1_CLK DO (U)SIM1 card clock 33 GND GND 34 UIM_DATA(I/O) USIM1_DATA IO (U)SIM1 card data 35 PERn1 USB_SS_RX_M AI USB 3.
5G Module Series RM502Q-GL Hardware Design 51 GND GND Ground 52 CLKREQ# PCIE_CLKREQ_N DO PCIe clock request. Active LOW. 53 REFCLKn PCIE_REFCLK_M AI, AO PCIe reference clock (-) 54 PEWAKE# PCIE_WAKE_N DO PCIe PME wake. Active LOW. 55 REFCLKp PCIE_REFCLK_P AI, AO PCIe reference clock (+) 56 NC RFFE1_CLK DO RFFE1 serial interface clock 57 GND GND 58 NC RFFE1_DATA DO RFFE1 serial interface data 1.8 V power domain 59 ANTCTL0 (O)(0/1.
5G Module Series RM502Q-GL Hardware Design 71 GND GND 72 3.3 V VCC 73 GND GND Ground PI Vmin = 3.135 V Vnorm = 3.7 V Vmax = 4.4 V Power supply Ground Vmin = 3.135 V Vnorm = 3.7 V Vmax = 4.4 V 74 3.3 V VCC PI Power supply 75 CONFIG_2 CONFIG_2 DO Not connected internally NOTE Keep 、all NC, reserved and unused pins unconnected. 3.3. Power Supply The following table shows pin definition of VCC pins and ground pins. Table 5: Definition of VCC and GND Pins Pin No.
5G Module Series RM502Q-GL Hardware Design Max Tx power Max Tx power VCC Voltage Ripple < 100mV Voltage Drop Min.3.135V Figure 3: Power Supply Limits during Radio Transmission The main power supply from an external system must be a single voltage source. To decrease voltage drop, a bypass capacitor of about 100 µF with low ESR (ESR = 0.7 Ω) should be used, and a multi-layer ceramic chip capacitor (MLCC) array also should be used due to its ultra-low ESR.
5G Module Series RM502Q-GL Hardware Design The following figure shows a reference design for +5 V input power source based on an DC-DC TPS54319. The typical output of the power supply is about 3.7 V and the maximum load current is 3 A. PWR_IN D1 TVS L1 1.5 μH U1 + R1 205k C2 C3 C1 470 μF 100 nF 33 pF PWR_EN 16 1 2 15 6 7 8 9 R2 80.6k VFB R3 10k R7 4.
5G Module Series RM502Q-GL Hardware Design When it is at high level, the module is powered on. 3.4.1.1. Turn on the Module with a Host GPIO It is recommended to use a host GPIO to control FULL_CARD_POWER_OFF#. A simple reference circuit is illustrated in the following figure. Host Module 1.8V or 3.3V FULL_CARD_POWER_OFF# GPIO 6 PMU R4 100k Note: The voltage of pin 6 should be no less than 1.19V when it is at HIGH level. Figure 6: Turn on the Module with a Host GPIO 3.4.1.2.
5G Module Series RM502Q-GL Hardware Design 3.4.1.3. Turn on the Module with Compatible Design The following figure shows a compatible design to turn on the module automatically after power-up or by host. Host Auto turn on 10k NM R1 R2 Turn on by host NM 0Ω Module VCC R1 10k FULL_CARD_POWER_OFF# GPIO 6 PMU R2 NM_0Ω R4 100k Notes: 1. The voltage of pin 6 should be no less than 1.19V when it is at HIGH level. 2. The VCC represents the power supply of the module.
5G Module Series RM502Q-GL Hardware Design internal LDO output) HIGH level, which is typically 68 ms. 3. t0 is the time interval between VCC and FULL_CARD_POWER_OFF# HIGH level. It could be 0 by turning on the module automatically as shown in Figure 7, or any other time decided by the host as shown in Figure 6. tbooting is the time interval between RFFE_VIO_1V8 HIGH level and the USIM_VDD power-on. 3.4.2. Turn off the Module 3.4.2.1.
5G Module Series RM502Q-GL Hardware Design VCC RESET_N(H) AT+QPOWD USB/PCIe USB/PCIe removed FULL_CARD_POWER_OFF# Module Status RUNNING Turn off procedure OFF Figure 11: Turn-off Timing through AT Command and FULL_CARD_POWER_OFF# For the circuit design of Figure 7, please cut off power supply of VCC after the module USB/PCIe is removed, as illustrated in Figure 11. Otherwise, the module will be powered on again.
5G Module Series RM502Q-GL Hardware Design 3.5. Reset RESET_N is an asynchronous and active low signal (1.8 V logic level). Whenever this pin is active, the modem will immediately be placed in a Power On Reset(POR) condition. CAUTION: Triggering the RESET# signal will lead to loss of all data in the modem and the removal of system drivers. It will also disconnect the modem from the network. Table 7: Definition of RESET_N Pin Pin No.
5G Module Series RM502Q-GL Hardware Design Host Module VDD 1.8V R1 100k RESET_N Reset pulse GPIO R4 10R 67 Reset Logic Q2 NMOS R5 100k 200-700 ms Figure 14: Reference Circuit of RESET_N with NMOS Driving Circuit Module VDD 1.8V R1 100k RESET_N 67 Reset Logic S1 TVS C1 33pF 200-700ms Note: The capacitor C1 is recommended to be less than 47pF. Figure 15: Reference Circuit of RESET_N with Button The reset scenario is illustrated in the following figure. VCC 700ms 200ms RESET_N VIL 0.
5G Module Series RM502Q-GL Hardware Design 3.6. (U)SIM Interfaces The (U)SIM interface circuitry meets ETSI and IMT-2000 requirements. Both Class B (3.0 V) and Class C (1.8 V) (U)SIM cards are supported, and Dual SIM Single Standby* function is supported. Table 8: Pin Definition of (U)SIM Interfaces Pin No. Pin Name I/O Description Comment 36 USIM1_VDD PO Power supply for (U)SIM1 card Class B (3.0 V) and Class C (1.8 V) 34 USIM1_DATA IO (U)SIM1 card data 1.8/3.
5G Module Series RM502Q-GL Hardware Design USIM1_VDD Module USIM1_DET USIM1_DATA 30 22R 32 22R VCC CLK 66 34 VPP RST CD 22R IO GND 33 pF USIM1_CLK 100 nF 10-20k 33 pF USIM1_RST 36 33 pF USIM1_VDD (U)SIM Card Connector GND TVS Note: All these resistors, capacitors and TVS should be close to (U)SIM card connector in PCB layout.
5G Module Series RM502Q-GL Hardware Design If (U)SIM card detection function is not needed, please keep USIM_DET unconnected. A reference circuit for (U)SIM card interface with a 6-pin (U)SIM card connector is illustrated in the following figure.
5G Module Series RM502Q-GL Hardware Design Please note that only USB 2.0 can be used for firmware upgrade currently. The following table shows the pin definition of USB interface. Table 9: Pin Definition of USB Interface Pin No. Pin Name I/O Description Comment 7 USB_DP AI/AO USB 2.0 differential data bus (+) 9 USB_DM AI/AO USB 2.0 differential data bus (-) 29 USB_SS_TX_M AO USB 3.1 transmit data (-) 31 USB_SS_TX_P AO USB 3.1 transmit data (+) 35 USB_SS_RX_M AI USB 3.
5G Module Series RM502Q-GL Hardware Design AC coupling capacitors C5 and C6 must be placed close to the host and close to each other. C1 and C2 have been integrated inside the module, so do not place these two capacitors on customers’ schematic and PCB. In order to ensure the signal integrity of USB 2.0 data traces, R1, R2, R3 and R4 must be placed close to the module, and the stubs must be minimized in PCB layout.
5G Module Series RM502Q-GL Hardware Design 3.8. PCIe Interface RM502Q-GL provides one integrated PCIe (Peripheral Component Interconnect Express) interface which complies with the PCI Express Base Specification, Revision 3.0 and supports up to 8 Gbps per lane. ⚫ ⚫ PCI Express Base Specification Revision 3.0 compliance Data rate up to 8 Gbps per lane The following table shows the pin definition of PCIe interface. Table 10: Pin Definition of PCIe Interface Pin No.
5G Module Series RM502Q-GL Hardware Design Host Module PCIE_REFCLK_P PCIE_REFCLK_P PCIE_REFCLK_M PCIE_REFCLK_M 53 55 PCIE_TX_P C5 220nF PCIE_RX_P 49 PCIE_TX_M C6 220nF PCIE_RX_M 47 PCIE_RX_P PCIE_TX_P 43 C1 220nF PCIE_RX_M PCIE_TX_M 41 C2 220nF BB PCIE_WAKE_N PCIE_CLKREQ_N PCIE_RST_N R1 100k R2 100k PCIE_WAKE_N 54 PCIE_CLKREQ_N 52 PCIE_RST_N 50 R3 100k VCC_IO_HOST Note: The voltage level of VCC_IO_HOST depends on the host side due to the open drain in pins 50, 52 and 54.
5G Module Series RM502Q-GL Hardware Design Module power-on or insertion detection VCC tpower-on 33 ms RESET_N System turn-on and booting VIH ≥ 1.19 V FULL_CARD_POWER_OFF# tturn-on 68 ms RFFE_VIO_1V8 23 ms PCIE_CLKREQ_N TPVPGL > 50 ms PCIE_RST_N TPERST#-CLK > 100 us PCIE_REFCLK Figure 23: PCIe Power-on Timing Requirements of the Module The following principles of PCIe interface design should be complied with, so as to meet PCIe V2.1 specification.
5G Module Series RM502Q-GL Hardware Design USB-AT-based PCIe Version ⚫ ⚫ ⚫ Support MBIM/QMI/QRTR/AT Support switch back to USB interface by AT command Support Non-X86 systems, need to be initiated in X86 system to meet BIOS PCIe early initial requirement When RM502Q-GL module works at USB-AT-based PCIe version, it supports MBIM/QMI/QRTR/AT, and can be switched back to USB version by AT command. But it does not support firmware upgrade by PCIE interface, therefore RM502Q-GL USB 2.
5G Module Series RM502Q-GL Hardware Design In auxiliary mode, the data is sampled on the falling edge of the PCM_CLK and transmitted on the rising edge. The PCM_SYNC rising edge represents the MSB. In this mode, PCM interface operates with a 256 kHz PCM_CLK and an 8 kHz, 50% duty cycle PCM_SYNC only. RM502Q-GL supports 16-bit linear data format.
5G Module Series RM502Q-GL Hardware Design Table 11: Pin Definition of PCM Interface* Pin No. Pin Name I/O Description Comment 20 PCM_CLK IO PCM data bit clock 1.8 V power domain In master mode, it is an output signal. In slave mode, it is an input signal. If unused, keep it open. 22 PCM_DIN DI PCM data input 1.8 V power domain 24 PCM_DOUT DO PCM data output 1.8 V power domain 28 PCM_SYNC IO PCM data frame sync 1.
5G Module Series RM502Q-GL Hardware Design 68 AP2SDX_STATUS DI Status indication from AP 1.8 V power domain NOTE “*” means under development. 3.10.1. W_DISABLE1#* RM502Q-GL provides a W_DISABLE1# pin to disable or enable airplane mode through hardware operation. The W_DISABLE1# pin is pulled up by default. Driving it low will set the module to airplane mode. In airplane mode, the RF function will be disabled. The RF function can also be enabled or disabled through software AT commands.
5G Module Series RM502Q-GL Hardware Design Table 14: GNSS Function Status W_DISABLE2# Level AT Commands GNSS Function Status High Level AT+QGPS=1 Enabled High Level AT+QGPSEND Low Level AT+QGPS=1 Low Level AT+QGPSEND Disabled A simple level shifter based on diodes is used on W_DISABLE1# pin and W_DISABLE2# pin which are pulled up to a 1.8 V voltage in the module, as shown in the following figure. So the control signals (GPIO) of the host device could be a 1.8 V or 3.3 V voltage level.
5G Module Series RM502Q-GL Hardware Design Host Module VCC R1 330Ω LED WWAN_LED# GPIO 10 PMU Note: This VCC could be the power supply of the module. Figure 27: WWAN_LED# Reference Circuit The following table shows the RF status indicated by WWAN_LED# signal.
5G Module Series RM502Q-GL Hardware Design Host Module VCC_IO_HOST R1 10k WAKE_ON_WAN# 23 GPIO H L BB 1s Wake up the host Note: The voltage level on VCC_IO_HOST depends on the host side due to the open drain in pin 23. Figure 28: WAKE_ON_WAN# Signal Reference Circuit 3.10.5. DPR* RM502Q-GL provides a DPR (Dynamic Power Reduction) pin for body SAR (Specific Absorption Rate) detection.
5G Module Series RM502Q-GL Hardware Design 3.11. Cellular/WLAN Interface* RM502Q-GL provides a cellular/WLAN COEX interface, the following table shows the pin definition of this interface. Table 18: Pin Definition of COEX Interface Pin No. Pin Name I/O Description Comment 62 COEX_RXD DI LTE/WLAN coexistence receive data 1.8 V power domain 64 COEX_TXD DO LTE/WLAN coexistence transmit data 1.8 V power domain 59 LAA_TX_EN DO Notification from SDR to WL when LTE transmitting 1.
5G Module Series RM502Q-GL Hardware Design 3.13. Configuration Pins RM502Q-GL provides four configuration pins, which are defined as below. Table 20: Definition of Configuration Pins Pin No. Pin Name I/O Power Domain Description 21 CONFIG_0 DO 0 NC internally 69 CONFIG_1 DO 0 Connected to GND internally 75 CONFIG_2 DO 0 NC internally 1 CONFIG_3 DO 0 NC internally The following figure shows a reference circuit of these four pins.
5G Module Series RM502Q-GL Hardware Design 4 GNSS Receiver 4.1. General Description RM502Q-GL includes a fully integrated global navigation satellite system solution that supports Gen9-Lite of Qualcomm (GPS, GLONASS, BeiDou/Compass, and Galileo). The module supports standard NMEA-0183 protocol, and outputs NMEA sentences at 1 Hz data update rate via USB interface by default. By default, RM502Q-GL GNSS engine is switched off. It has to be switched on via AT command.
5G Module Series RM502Q-GL Hardware Design 4.2. GNSS Performance The following table shows GNSS performance of RM502Q-GL series module. Table 22: GNSS Performance Parameter Sensitivity (GNSS) Description Conditions Typ.
5G Module Series RM502Q-GL Hardware Design 5 Antenna Connection RM502Q-GL provides four antenna interfaces, the impedance of antenna port is 50 Ω. 5.1. RF Antenna Interfaces 5.1.1. Antenna Pin Definition The pin definition of RF antenna interfaces is shown below.
5G Module Series RM502Q-GL Hardware Design 5.1.2.
5G Module Series RM502Q-GL Hardware Design IMT-E (2600) 2500–2570 2620–2690 B7 – – n7 EGSM (950) 880–915 925–960 B8 – B8 n8 J1700 1750–1785 1845–1880 B9 – B9 – 700 lower A–C 699–716 729–746 B12 – – n12 700 upper C 777–787 746–756 B13 – – – 700 D 788–798 758–768 B14 – – – B17 704–716 734–746 B17 – – – B18 815–830 860–875 B18 – – – B19 830–845 875–890 B19 – B19 – EU800 832–862 791–821 B20 – – n20 PCS + G 1850–1915 1930–1995 B25 – – –
5G Module Series RM502Q-GL Hardware Design n78 3300–3800 3300–3800 – – – n78 5.1.4. Reference Design of RF Antenna Interface A reference design of antenna interface is shown as below. A π-type matching circuit should be reserved for better RF performance. The capacitors are not mounted by default. Module ANT0 R1 0Ω C1 NM ANT3 C2 NM R4 0Ω C7 NM C8 NM Figure 30: Reference Circuit of RF Antenna NOTES 1. 2. 3. 4. 5. 6. Keep the characteristic impedance for antenna trace as 50 Ω.
5G Module Series RM502Q-GL Hardware Design Table 26: GNSS Frequency Type Frequency Unit GPS/Galileo/QZSS 1575.42 ±1.023 (L1) MHz Galileo 1575.42 ±2.046 (E1) MHz QZSS 1575.42 (L1) MHz GLONASS 1597.5–1605.8 MHz BeiDou 1561.098 ±2.046 MHz NOTES 1. 2. 3. 4. 5. Keep the characteristic impedance for ANT_GNSS trace as 50 Ω. Place the π-type matching components as close to the antenna as possible.
5G Module Series RM502Q-GL Hardware Design Figure 31: Microstrip Design on a 2-layer PCB Figure 32: Coplanar Waveguide Design on a 2-layer PCB Figure 33: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground) RM502Q-GL_Hardware_Design 54 / 77
5G Module Series RM502Q-GL Hardware Design Figure 34: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground) In order to ensure RF performance and reliability, the following principles should be complied with in RF layout design: ⚫ ⚫ ⚫ ⚫ ⚫ Use impedance simulation tool to control the characteristic impedance of RF traces as 50 Ω. The GND pins adjacent to RF pins should not be designed as thermal relief pads, and should be fully connected to ground.
5G Module Series RM502Q-GL Hardware Design Figure 35: Antenna Connectors on the Module 5.4.
5G Module Series RM502Q-GL Hardware Design 5.5. Antenna Installation 5.5.1. Antenna Requirements The following table shows the requirements on WCDMA, LTE, 5G NR antenna and GNSS antenna. Table 28: Antenna Requirements Type Requirements GNSS Frequency range: 1559–1606 MHz Polarization: RHCP or linear VSWR: < 2 (Typ.) Passive antenna gain: >0 dBi WCDMA/LTE/5G NR VSWR: ≤ 3 Efficiency: > 30% Input Impedance: 50 Ω WCDMA LB, LTE LB: Cable insertion loss: < 1 dB WCDMA MB, LTE MB: Cable insertion loss: < 1.
5G Module Series RM502Q-GL Hardware Design Figure 36: RM502Q-GL RF Connector Dimensions (Unit: mm) Table 29: Major Specifications of the RF Connector Item Specification Nominal Frequency Range DC to 6 GHz Nominal Impedance 50 Ω Temperature Rating -40°C to +85°C Voltage Standing Wave Ratio (VSWR) Meet the requirements of: Max 1.3 (DC–3 GHz) Max 1.45 (3–6 GHz) The receptacle RF connector used in conjunction with RM502Q-GL will accept two types of mating plugs that will meet a maximum height of 1.
5G Module Series RM502Q-GL Hardware Design Figure 38: Connection between RF Connector and Mating Plug Using Ø0.81 mm Coaxial Cable The following figure illustrates the connection between the receptacle RF connector on RM502Q-GL and the mating plug using a Ø1.13 mm coaxial cable. Figure 39: Connection between RF Connector and Mating Plug Using Ø1.
5G Module Series RM502Q-GL Hardware Design 6 Electrical, Reliability and Radio Characteristics 6.1. Absolute Maximum Ratings Absolute maximum ratings for power supply and voltage on digital and analog pins of the module are listed in the following table. Table 30: Absolute Maximum Ratings Parameter Min. Max. Unit VCC -0.3 4.7 V Voltage at Digital Pins -0.3 2.3 V 6.2. Power Supply Requirements The typical input voltage of RM502Q-GL is 3.7 V, as specified by PCIe M.
5G Module Series RM502Q-GL Hardware Design 6.3. I/O Requirements Table 32: I/O Requirements Parameter Description Min. Max. Unit VIH Input high voltage 0.7 × VDD18 1) VDD18 +0.3 V VIL Input low voltage -0.3 0.3 × VDD18 V VOH Output high voltage VDD18-0.5 VDD18 V VOL Output low voltage 0 0.4 V NOTE 1) V DD18 is the I/O power domain of the module. 6.4. Operation and Storage Temperatures Table 33: Operation and Storage Temperatures Parameter Min. Typ. Max.
5G Module Series RM502Q-GL Hardware Design 6.5. Current Consumption Table 34: RM502Q-GL Current Consumption Parameter Description Conditions Typ.
5G Module Series RM502Q-GL Hardware Design IVBAT IVBAT WCDMA data transfer (GNSS OFF) LTE data transfer (GNSS OFF) WCDMA B3 HSDPA CH1338 @ 23 dBm TBD mA WCDMA B3 HSUPA CH1338 @ 23 dBm TBD mA WCDMA B4 HSDPA CH1638 @ 23 dBm TBD mA WCDMA B4 HSUPA CH1638 @ 23 dBm TBD mA WCDMA B5 HSDPA CH4407 @ 23 dBm TBD mA WCDMA B5 HSUPA CH4407 @ 23 dBm TBD mA WCDMA B6 HSDPA CH4400 @ 23 dBm TBD mA WCDMA B6 HSUPA CH4400 @ 23 dBm TBD mA WCDMA B8 HSDPA CH3012 @ 23 dBm TBD mA WCDMA B8 HSUPA CH3012 @
5G Module Series RM502Q-GL Hardware Design IVBAT IVBAT LTE Data transfer (GNSS OFF) 5G NR data transfer (GNSS OFF) LTE-FDD B20 CH6300 @ 23 dBm TBD mA LTE-FDD B25 CH8365 @ 23 dBm TBD mA LTE-FDD B26 CH8865 @ 23 dBm TBD mA LTE-FDD B28 CH9435 @ 23 dBm TBD mA LTE-FDD B30 CH9820 @ 23 dBm TBD mA LTE-TDD B34 CH36275 @ 23 dBm TBD mA LTE-TDD B38 CH38000 @ 23 dBm TBD mA LTE-TDD B39 CH38450 @ 23 dBm TBD mA LTE-TDD B40 CH39150 @ 23 dBm TBD mA LTE-TDD B41 CH40620 @ 23 dBm TBD mA LTE-TDD
5G Module Series RM502Q-GL Hardware Design IVBAT 5G NR data transfer (GNSS OFF) 5G NR-FDD n1 CH433000 @ 23 dBm TBD mA 5G NR-FDD n2 CH387000 @ 23 dBm TBD mA 5G NR-FDD n2 CH392000 @ 23 dBm TBD mA 5G NR-FDD n2 CH397000 @ 23 dBm TBD mA 5G NR-FDD n3 CH362000 @ 23 dBm TBD mA 5G NR-FDD n3 CH368500 @ 23 dBm TBD mA 5G NR-FDD n3 CH375000 @ 23 dBm TBD mA 5G NR-FDD n5 CH174800 @ 23 dBm TBD mA 5G NR-FDD n5 CH176300 @ 23 dBm TBD mA 5G NR-FDD n5 CH177800 @ 23 dBm TBD mA 5G NR-FDD n7 CH5250
5G Module Series RM502Q-GL Hardware Design IVBAT IVBAT 5G NR data transfer (GNSS OFF) WCDMA voice call 5G NR-TDD n38 CH519000 @ 23 dBm TBD mA 5G NR-TDD n38 CH523000 @ 23 dBm TBD mA 5G NR-TDD n40 CH461000 @ 23 dBm TBD mA 5G NR-TDD n40 CH470000 @ 23 dBm TBD mA 5G NR-TDD n40 CH479000 @ 23 dBm TBD mA 5G NR-FDD n66 CH423000 @ 23 dBm TBD mA 5G NR-FDD n66 CH429000 @ 23 dBm TBD mA 5G NR-FDD n66 CH435000 @ 23 dBm TBD mA 5G NR-FDD n71 CH124400 @ 23 dBm TBD mA 5G NR-FDD n71 CH126900 @ 2
5G Module Series RM502Q-GL Hardware Design 6.6. RF Output Power The following table shows the RF output power of RM502Q-GL module. Table 35: RF Output Power Mode Frequency Max. Min.
5G Module Series RM502Q-GL Hardware Design Table 36: RM502Q-GL Conducted RF Receiving Sensitivity Mode WCDMA WCDMA Frequency Primary Diversity SIMO1) 3GPP (SIMO) WCDMA B1 TBD TBD TBD -106.7 dBm WCDMA B2 TBD TBD TBD -104.7 dBm WCDMA B3 TBD TBD TBD -103.7 dBm WCDMA B4 TBD TBD TBD -106.7 dBm WCDMA B5 TBD TBD TBD -104.7 dBm WCDMA B8 TBD TBD TBD -103.7 dBm WCDMA B19 TBD TBD TBD -104.7 dBm LTE-FDD B1 (10 MHz) TBD TBD TBD -96.
5G Module Series RM502Q-GL Hardware Design LTE-FDD B25 (10 MHz) TBD TBD TBD -92.8 dBm LTE-FDD B26 (10 MHz) TBD TBD TBD -93.8 dBm LTE-FDD B28 (10 MHz) TBD TBD TBD -94.8 dBm LTE-FDD B30 (10 MHz) TBD TBD TBD -95.3 dBm LTE-FDD B32 (10 MHz) TBD TBD TBD -95.3 dBm LTE-TDD B34 (10 MHz) TBD TBD TBD -96.3 dBm LTE-TDD B38 (10 MHz) TBD TBD TBD -96.3 dBm LTE-TDD B39 (10 MHz) TBD TBD TBD -96.3 dBm LTE-TDD B40 (10 MHz) TBD TBD TBD -96.
5G Module Series RM502Q-GL Hardware Design 5G NR-TDD n41 (20 MHz) (SCS: 30 kHz) TBD TBD TBD -92.0 dBm 5G NR-FDD n66 (20 MHz) (SCS: 15 kHz) TBD TBD TBD -93.5 dBm 5G NR-FDD n71 (10 MHz) (SCS: 15 kHz) TBD TBD TBD -94.0 dBm 5G NR-TDD n77 (20 MHz) (SCS: 30 kHz) TBD TBD TBD -92.9 dBm 5G NR-TDD n78 (20 MHz) (SCS: 30 kHz) TBD TBD TBD -92.
5G Module Series RM502Q-GL Hardware Design conductive compounds between the module and the main PCB for thermal dissipation. The thermal dissipation area (i.e. the area for adding thermal pad) is shown as below. The dimensions are measured in mm. Figure 40: Thermal Dissipation Area on Bottom Side of Module (Bottom View) There are other measures to enhance heat dissipation performance: ⚫ ⚫ ⚫ ⚫ ⚫ ⚫ ⚫ ⚫ Add ground vias as many as possible on PCB. Maximize airflow over/around the module.
5G Module Series RM502Q-GL Hardware Design NOTE For more detailed guidelines on thermal design, please refer to document [5].
5G Module Series RM502Q-GL Hardware Design 7 Mechanical Dimensions and Packaging This chapter mainly describes mechanical dimensions and packaging specifications of RM502Q-GL module. All dimensions are measured in mm, and the tolerances are ±0.05 mm unless otherwise specified. 7.1.
5G Module Series RM502Q-GL Hardware Design 7.2. Top and Bottom Views of the Module Top View Bottom View Figure 42: Top and Bottom Views of the Module NOTE These are rendering images of RM502Q-GL module. For authentic appearance, please refer to the module that you receive from Quectel. 7.3. M.2 Connector RM502Q-GL adopts a standard PCI Express M.2 connector which compiles with the directives and standards listed in document [4].
5G Module Series RM502Q-GL Hardware Design 7.4. Packaging RM502Q-GL modules are packaged in trays. The following figure shows the tray size. Figure 43: Tray Size (Unit: mm) Each tray contains 10 modules. The smallest package contains 100 modules. Tray packaging procedures are as below. 1. 2. 3. 4. 5. 6. Use 10 trays to package 100 modules at a time (tray size: 247 mm × 172 mm). Place an empty tray on the top of the 10-tray stack.
5G Module Series RM502Q-GL Hardware Design 8 Appendix References Table 38: Related Documents SN.
5G Module Series RM502Q-GL Hardware Design GLONASS Global Navigation Satellite System (Russia) GNSS Global Navigation Satellite System GPS Global Positioning System GSM Global System for Mobile Communications HR Half Rate HSPA High Speed Packet Access HSUPA High Speed Uplink Packet Access kbps Kilo Bits Per Second LAA License Assisted Access LED Light Emitting Diode LTE Long Term Evolution Mbps Mega Bits Per Second ME Mobile Equipment MIMO Multiple-Input Multiple-Output MLCC Mu
5G Module Series RM502Q-GL Hardware Design RF Radio Frequency Rx Receive SAR Specific Absorption Rate SMS Short Message Service Tx Transmit UART Universal Asynchronous Receiver & Transmitter UL Uplink URC Unsolicited Result Code USB Universal Serial Bus (U)SIM (Universal) Subscriber Identity Module VIH Input High Voltage Level VIL Input Low Voltage Level VOH Output High Voltage Level VOL Output Low Voltage Level WCDMA Wideband Code Division Multiple Access Installation enginee
OEM/Integrators Installation Manual Important Notice to OEM integrators 1. This module is limited to OEM installation ONLY. 2. This module is limited to installation in mobile or fixed applications, according to Part 2.1091(b). 3. The separate approval is required for all other operating configurations, including portable configurations with respect to Part 2.1093 and different antenna configurations 4. For FCC Part 15.
Antenna (1) The antenna must be installed such that 20 cm is maintained between the antenna and users, (2) The transmitter module may not be co-located with any other transmitter or antenna. In the event that these conditions cannot be met (for example certain laptop configurations or co-location with another transmitter), then the FCC/IC authorization is no longer considered valid and the FCC ID/IC ID cannot be used on the final product.
Federal Communication Commission Interference Statement This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules.
This device is intended only for OEM integrators under the following conditions: (For module device use) 1) The antenna must be installed such that 20 cm is maintained between the antenna and users, and 2) The transmitter module may not be co-located with any other transmitter or antenna. As long as 2 conditions above are met, further transmitter test will not be required.
Industry Canada Statement This device complies with Industry Canada’s licence-exempt RSSs. Operation is subject to the following two conditions: (1) This device may not cause interference; and (2) This device must accept any interference, including interference that may cause undesired operation of the device. Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence.
Cet appareil est conçu uniquement pour les intégrateurs OEM dans les conditions suivantes: (Pour utilisation de dispositif module) 1) L'antenne doit être installée de telle sorte qu'une distance de 20 cm est respectée entre l'antenne et les utilisateurs, et 2) Le module émetteur peut ne pas être coïmplanté avec un autre émetteur ou antenne. Tant que les 2 conditions ci-dessus sont remplies, des essais supplémentaires sur l'émetteur ne seront pas nécessaires.
Manual Information to the End User The OEM integrator has to be aware not to provide information to the end user regarding how to install or remove this RF module in the user’s manual of the end product which integrates this module. The end user manual shall include all required regulatory information/warning as show in this manual.
